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@@ -27,7 +27,6 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 0x2000
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#else
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-#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE 0x20000
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@@ -41,6 +40,8 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_DDR_CLK_FREQ 100000000
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#else
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+#define CONFIG_QIXIS_I2C_ACCESS
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+#define CONFIG_SYS_I2C_EARLY_INIT
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
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#endif
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@@ -89,13 +90,14 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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+ FTIM0_NOR_TAVDS(0x6) | \
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FTIM0_NOR_TEAHC(0x5))
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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- FTIM1_NOR_TRAD_NOR(0x1a) |\
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+ FTIM1_NOR_TRAD_NOR(0x1a) | \
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
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- FTIM2_NOR_TCH(0x4) | \
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- FTIM2_NOR_TWPH(0x0E) | \
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+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
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+ FTIM2_NOR_TCH(0x8) | \
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+ FTIM2_NOR_TWPH(0xe) | \
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FTIM2_NOR_TWP(0x1c))
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#define CONFIG_SYS_NOR_FTIM3 0x04000000
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#define CONFIG_SYS_IFC_CCR 0x01000000
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@@ -197,7 +199,7 @@ unsigned long get_board_ddr_clk(void);
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| CSPR_MSEL_GPCM \
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| CSPR_V)
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-#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
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+#define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
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#else
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@@ -226,7 +228,7 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
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#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
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-#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
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+#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
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#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
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#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
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@@ -262,13 +264,13 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
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#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
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-#define CONFIG_SYS_CSPR3_FINAL CONFIG_SYS_FPGA_CSPR_FINAL
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-#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
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+#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
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+#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
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#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
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-#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_CS_FTIM0
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-#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_CS_FTIM1
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-#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_CS_FTIM2
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-#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_CS_FTIM3
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+#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
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+#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
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+#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
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+#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
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#endif
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#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
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