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@@ -144,6 +144,12 @@
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#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0)
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/* Bit definitions for Clock gating Register*/
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+#define MXC_CCM_CGR_CG_MASK 0x3
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+#define MXC_CCM_CGR_CG_OFF 0x0
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+#define MXC_CCM_CGR_CG_RUN_ON 0x1
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+#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2
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+#define MXC_CCM_CGR_CG_ON 0x3
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+
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#define MXC_CCM_CGR0_ASRC_OFFSET 0
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#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0)
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#define MXC_CCM_CGR0_ATA_OFFSET 2
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