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@@ -83,6 +83,47 @@ u32 get_cpu_rev(void)
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return (type << 12) | (reg + 0x10);
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}
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+/*
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+ * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
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+ * defines a 2-bit SPEED_GRADING
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+ */
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+#define OCOTP_CFG3_SPEED_SHIFT 16
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+#define OCOTP_CFG3_SPEED_800MHZ 0
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+#define OCOTP_CFG3_SPEED_850MHZ 1
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+#define OCOTP_CFG3_SPEED_1GHZ 2
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+#define OCOTP_CFG3_SPEED_1P2GHZ 3
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+
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+u32 get_cpu_speed_grade_hz(void)
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+{
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+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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+ struct fuse_bank *bank = &ocotp->bank[0];
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+ struct fuse_bank0_regs *fuse =
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+ (struct fuse_bank0_regs *)bank->fuse_regs;
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+ uint32_t val;
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+
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+ val = readl(&fuse->cfg3);
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+ val >>= OCOTP_CFG3_SPEED_SHIFT;
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+ val &= 0x3;
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+
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+ switch (val) {
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+ /* Valid for IMX6DQ */
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+ case OCOTP_CFG3_SPEED_1P2GHZ:
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+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
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+ return 1200000000;
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+ /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
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+ case OCOTP_CFG3_SPEED_1GHZ:
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+ return 996000000;
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+ /* Valid for IMX6DQ */
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+ case OCOTP_CFG3_SPEED_850MHZ:
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+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
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+ return 852000000;
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+ /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
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+ case OCOTP_CFG3_SPEED_800MHZ:
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+ return 792000000;
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+ }
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+ return 0;
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+}
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+
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#ifdef CONFIG_REVISION_TAG
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u32 __weak get_board_rev(void)
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{
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