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@@ -465,23 +465,21 @@ static void set_sdr_mp_pacing(void)
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static void set_sdr_mp_threshold(void)
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{
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- debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
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- clrsetbits_le32(&sdr_ctrl->mp_threshold0,
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- SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK,
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- CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
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+ const u32 mp_threshold0 =
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+ (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
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SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB);
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-
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- clrsetbits_le32(&sdr_ctrl->mp_threshold1,
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- SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK,
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- CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
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+ const u32 mp_threshold1 =
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+ (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
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SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB);
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-
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- clrsetbits_le32(&sdr_ctrl->mp_threshold2,
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- SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK,
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- CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
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+ const u32 mp_threshold2 =
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+ (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
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SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB);
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-}
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+ debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
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+ writel(mp_threshold0, &sdr_ctrl->mp_threshold0);
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+ writel(mp_threshold1, &sdr_ctrl->mp_threshold1);
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+ writel(mp_threshold2, &sdr_ctrl->mp_threshold2);
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+}
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/* Function to initialize SDRAM MMR */
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unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
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