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@@ -9,7 +9,7 @@
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#include <asm/io.h>
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#include <asm/arch/gxbb.h>
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#include <asm/arch/sm.h>
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-#include <phy.h>
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+#include <asm/arch/eth.h>
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#define EFUSE_SN_OFFSET 20
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#define EFUSE_SN_SIZE 16
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@@ -27,17 +27,10 @@ int misc_init_r(void)
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char serial[EFUSE_SN_SIZE];
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ssize_t len;
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- /* Set RGMII mode */
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- setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
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- GXBB_ETH_REG_0_TX_PHASE(1) |
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- GXBB_ETH_REG_0_TX_RATIO(4) |
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- GXBB_ETH_REG_0_PHY_CLK_EN |
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- GXBB_ETH_REG_0_CLK_EN);
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+ meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
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/* Enable power and clock gate */
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setbits_le32(GXBB_GCLK_MPEG_0, GXBB_GCLK_MPEG_0_I2C);
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- setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
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- clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
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/* Reset PHY on GPIOZ_14 */
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clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
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