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@@ -14,7 +14,7 @@
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#include <asm/arch/pch.h>
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#include <asm/arch/sandybridge.h>
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-static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev)
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+static void sandybridge_setup_lpc_bars(pci_dev_t lpc_dev)
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{
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/* Setting up Southbridge. In the northbridge code. */
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debug("Setting up static southbridge registers\n");
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@@ -26,30 +26,31 @@ static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev)
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debug("Disabling watchdog reboot\n");
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setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
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outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
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+}
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+static void sandybridge_setup_northbridge_bars(struct udevice *dev)
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+{
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/* Set up all hardcoded northbridge BARs */
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debug("Setting up static registers\n");
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- x86_pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1);
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- x86_pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
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- x86_pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1);
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- x86_pci_write_config32(pch_dev, MCHBAR + 4,
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- (0LL + DEFAULT_MCHBAR) >> 32);
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+ dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1);
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+ dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
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+ dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1);
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+ dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
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/* 64MB - busses 0-63 */
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- x86_pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
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- x86_pci_write_config32(pch_dev, PCIEXBAR + 4,
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- (0LL + DEFAULT_PCIEXBAR) >> 32);
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- x86_pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1);
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- x86_pci_write_config32(pch_dev, DMIBAR + 4,
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- (0LL + DEFAULT_DMIBAR) >> 32);
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+ dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
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+ dm_pci_write_config32(dev, PCIEXBAR + 4,
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+ (0LL + DEFAULT_PCIEXBAR) >> 32);
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+ dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1);
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+ dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
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/* Set C0000-FFFFF to access RAM on both reads and writes */
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- x86_pci_write_config8(pch_dev, PAM0, 0x30);
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- x86_pci_write_config8(pch_dev, PAM1, 0x33);
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- x86_pci_write_config8(pch_dev, PAM2, 0x33);
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- x86_pci_write_config8(pch_dev, PAM3, 0x33);
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- x86_pci_write_config8(pch_dev, PAM4, 0x33);
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- x86_pci_write_config8(pch_dev, PAM5, 0x33);
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- x86_pci_write_config8(pch_dev, PAM6, 0x33);
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+ dm_pci_write_config8(dev, PAM0, 0x30);
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+ dm_pci_write_config8(dev, PAM1, 0x33);
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+ dm_pci_write_config8(dev, PAM2, 0x33);
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+ dm_pci_write_config8(dev, PAM3, 0x33);
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+ dm_pci_write_config8(dev, PAM4, 0x33);
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+ dm_pci_write_config8(dev, PAM5, 0x33);
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+ dm_pci_write_config8(dev, PAM6, 0x33);
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}
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static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
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@@ -122,10 +123,6 @@ void sandybridge_early_init(int chipset_type)
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{
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pci_dev_t pch_dev = PCH_DEV;
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pci_dev_t video_dev = PCH_VIDEO_DEV;
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- pci_dev_t lpc_dev = PCH_LPC_DEV;
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-
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- /* Setup all BARs required for early PCIe and raminit */
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- sandybridge_setup_bars(pch_dev, lpc_dev);
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/* Device Enable */
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x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
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@@ -154,6 +151,10 @@ static int bd82x6x_northbridge_probe(struct udevice *dev)
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dm_pci_write_config8(dev, 0xf3, reg8);
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}
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+ sandybridge_setup_lpc_bars(PCH_LPC_DEV);
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+
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+ sandybridge_setup_northbridge_bars(dev);
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+
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return 0;
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}
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