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@@ -60,7 +60,7 @@
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#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
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#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
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-#if defined(CONFIG_T1024RDB)
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+#if defined(CONFIG_TARGET_T1024RDB)
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg
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#elif defined(CONFIG_TARGET_T1023RDB)
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg
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@@ -79,7 +79,7 @@
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#endif
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-#if defined(CONFIG_T1024RDB)
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+#if defined(CONFIG_TARGET_T1024RDB)
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg
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#elif defined(CONFIG_TARGET_T1023RDB)
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg
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@@ -98,7 +98,7 @@
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#endif
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-#if defined(CONFIG_T1024RDB)
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+#if defined(CONFIG_TARGET_T1024RDB)
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg
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#elif defined(CONFIG_TARGET_T1023RDB)
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg
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@@ -175,7 +175,7 @@
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#define CONFIG_ENV_SPI_MODE 0
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#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
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#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
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-#if defined(CONFIG_T1024RDB)
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+#if defined(CONFIG_TARGET_T1024RDB)
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#elif defined(CONFIG_TARGET_T1023RDB)
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#define CONFIG_ENV_SECT_SIZE 0x40000
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@@ -190,7 +190,7 @@
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#define CONFIG_SYS_EXTRA_ENV_RELOC
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SIZE 0x2000
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-#if defined(CONFIG_T1024RDB)
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+#if defined(CONFIG_TARGET_T1024RDB)
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#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#elif defined(CONFIG_TARGET_T1023RDB)
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#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
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@@ -271,7 +271,7 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
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#define CONFIG_FSL_DDR_INTERACTIVE
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-#if defined(CONFIG_T1024RDB)
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+#if defined(CONFIG_TARGET_T1024RDB)
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#define CONFIG_DDR_SPD
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#define CONFIG_SYS_FSL_DDR3
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#define CONFIG_SYS_SPD_BUS_NUM 0
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@@ -301,7 +301,7 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
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/* NOR Flash Timing Params */
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-#if defined(CONFIG_T1024RDB)
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+#if defined(CONFIG_TARGET_T1024RDB)
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#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
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#elif defined(CONFIG_TARGET_T1023RDB)
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#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
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@@ -330,7 +330,7 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
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-#ifdef CONFIG_T1024RDB
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+#ifdef CONFIG_TARGET_T1024RDB
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/* CPLD on IFC */
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#define CONFIG_SYS_CPLD_BASE 0xffdf0000
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#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
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@@ -369,7 +369,7 @@ unsigned long get_board_ddr_clk(void);
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| CSPR_V)
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#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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-#if defined(CONFIG_T1024RDB)
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+#if defined(CONFIG_TARGET_T1024RDB)
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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@@ -706,7 +706,7 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_DPAA_FMAN
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-#ifdef CONFIG_T1024RDB
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+#ifdef CONFIG_TARGET_T1024RDB
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#define CONFIG_QE
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#define CONFIG_U_QE
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#endif
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@@ -730,7 +730,7 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
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#elif defined(CONFIG_NAND)
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#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
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-#if defined(CONFIG_T1024RDB)
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+#if defined(CONFIG_TARGET_T1024RDB)
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#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#elif defined(CONFIG_TARGET_T1023RDB)
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@@ -761,7 +761,7 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_PHYLIB_10G
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#define CONFIG_PHY_REALTEK
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#define CONFIG_PHY_AQUANTIA
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-#if defined(CONFIG_T1024RDB)
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+#if defined(CONFIG_TARGET_T1024RDB)
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#define RGMII_PHY1_ADDR 0x2
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#define RGMII_PHY2_ADDR 0x6
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#define SGMII_AQR_PHY_ADDR 0x2
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