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@@ -41,14 +41,19 @@ u32 get_cpu_rev(void)
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if (type != MXC_CPU_MX6SL) {
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reg = readl(&anatop->digprog);
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+ struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
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+ u32 cfg = readl(&scu->config) & 3;
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type = ((reg >> 16) & 0xff);
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if (type == MXC_CPU_MX6DL) {
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- struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
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- u32 cfg = readl(&scu->config) & 3;
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-
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if (!cfg)
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type = MXC_CPU_MX6SOLO;
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}
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+
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+ if (type == MXC_CPU_MX6Q) {
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+ if (cfg == 1)
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+ type = MXC_CPU_MX6D;
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+ }
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+
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}
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reg &= 0xff; /* mx6 silicon revision */
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return (type << 12) | (reg + 0x10);
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@@ -62,6 +67,9 @@ u32 __weak get_board_rev(void)
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if (type == MXC_CPU_MX6SOLO)
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cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
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+ if (type == MXC_CPU_MX6D)
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+ cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
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+
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return cpurev;
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}
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#endif
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