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@@ -840,6 +840,37 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)
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debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
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}
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+/**
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+ * rw_mgr_mem_init_load_regs() - Load instruction registers
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+ * @cntr0: Counter 0 value
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+ * @cntr1: Counter 1 value
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+ * @cntr2: Counter 2 value
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+ * @jump: Jump instruction value
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+ *
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+ * Load instruction registers.
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+ */
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+static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
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+{
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+ uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
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+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
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+
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+ /* Load counters */
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+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
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+ &sdr_rw_load_mgr_regs->load_cntr0);
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+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
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+ &sdr_rw_load_mgr_regs->load_cntr1);
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+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
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+ &sdr_rw_load_mgr_regs->load_cntr2);
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+
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+ /* Load jump address */
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+ writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
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+ writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
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+ writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
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+
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+ /* Execute count instruction */
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+ writel(jump, grpaddr);
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+}
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+
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static void rw_mgr_mem_initialize(void)
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{
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uint32_t r;
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@@ -875,25 +906,9 @@ static void rw_mgr_mem_initialize(void)
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* One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
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* b = 6A
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*/
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-
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- /* Load counters */
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- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL),
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- &sdr_rw_load_mgr_regs->load_cntr0);
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- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL),
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- &sdr_rw_load_mgr_regs->load_cntr1);
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- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL),
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- &sdr_rw_load_mgr_regs->load_cntr2);
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-
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- /* Load jump address */
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- writel(RW_MGR_INIT_RESET_0_CKE_0,
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- &sdr_rw_load_jump_mgr_regs->load_jump_add0);
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- writel(RW_MGR_INIT_RESET_0_CKE_0,
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- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
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- writel(RW_MGR_INIT_RESET_0_CKE_0,
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- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
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-
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- /* Execute count instruction */
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- writel(RW_MGR_INIT_RESET_0_CKE_0, grpaddr);
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+ rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
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+ SEQ_TINIT_CNTR2_VAL,
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+ RW_MGR_INIT_RESET_0_CKE_0);
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/* indicate that memory is stable */
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writel(1, &phy_mgr_cfg->reset_mem_stbl);
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@@ -912,24 +927,9 @@ static void rw_mgr_mem_initialize(void)
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* One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
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* b = FF
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*/
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-
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- /* Load counters */
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- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL),
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- &sdr_rw_load_mgr_regs->load_cntr0);
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- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL),
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- &sdr_rw_load_mgr_regs->load_cntr1);
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- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL),
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- &sdr_rw_load_mgr_regs->load_cntr2);
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-
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- /* Load jump address */
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- writel(RW_MGR_INIT_RESET_1_CKE_0,
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- &sdr_rw_load_jump_mgr_regs->load_jump_add0);
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- writel(RW_MGR_INIT_RESET_1_CKE_0,
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- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
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- writel(RW_MGR_INIT_RESET_1_CKE_0,
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- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
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-
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- writel(RW_MGR_INIT_RESET_1_CKE_0, grpaddr);
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+ rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
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+ SEQ_TRESET_CNTR2_VAL,
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+ RW_MGR_INIT_RESET_1_CKE_0);
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/* bring up clock enable */
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