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@@ -365,18 +365,6 @@ static void init_bandgap(void)
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}
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}
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}
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}
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-#ifdef CONFIG_MX6SL
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-static void set_preclk_from_osc(void)
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-{
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- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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- u32 reg;
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-
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- reg = readl(&mxc_ccm->cscmr1);
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- reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
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- writel(reg, &mxc_ccm->cscmr1);
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-}
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-#endif
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-
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int arch_cpu_init(void)
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int arch_cpu_init(void)
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{
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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@@ -444,9 +432,8 @@ int arch_cpu_init(void)
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}
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}
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/* Set perclk to source from OSC 24MHz */
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/* Set perclk to source from OSC 24MHz */
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-#if defined(CONFIG_MX6SL)
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- set_preclk_from_osc();
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-#endif
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+ if (is_mx6sl())
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+ setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
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imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
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imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
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