x86: Enable DM RTC support for all x86 boards

Add a RTC node in the device tree to enable DM RTC support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
(Squashed in 'x86: Fix RTC build error on ivybridge')

arch/x86/cpu/ivybridge/lpc.c

@@ -252,7 +252,6 @@ static void pch_rtc_init(pci_dev_t dev)
 	/* TODO: Handle power failure */
 	if (rtc_failed)
 		printf("RTC power failed\n");
-	rtc_init();
 }
 
 /* CougarPoint PCH Power Management init */

arch/x86/cpu/ivybridge/sdram.c

@@ -128,6 +128,14 @@ static int get_mrc_entry(struct udevice **devp, struct fmap_entry *entry)
 static int read_seed_from_cmos(struct pei_data *pei_data)
 {
 	u16 c1, c2, checksum, seed_checksum;
+	struct udevice *dev;
+	int rcode = 0;
+
+	rcode = uclass_get_device(UCLASS_RTC, 0, &dev);
+	if (rcode) {
+		debug("Cannot find RTC: err=%d\n", rcode);
+		return -ENODEV;
+	}
 
 	/*
 	 * Read scrambler seeds from CMOS RAM. We don't want to store them in
@@ -135,11 +143,11 @@ static int read_seed_from_cmos(struct pei_data *pei_data)
 	 * the flash too much. So we store these in CMOS and the large MRC
 	 * data in SPI flash.
 	 */
-	pei_data->scrambler_seed = rtc_read32(CMOS_OFFSET_MRC_SEED);
+	rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed);
 	debug("Read scrambler seed    0x%08x from CMOS 0x%02x\n",
 	      pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
 
-	pei_data->scrambler_seed_s3 = rtc_read32(CMOS_OFFSET_MRC_SEED_S3);
+	rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3, &pei_data->scrambler_seed_s3);
 	debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
 	      pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
 
@@ -150,8 +158,8 @@ static int read_seed_from_cmos(struct pei_data *pei_data)
 				 sizeof(u32));
 	checksum = add_ip_checksums(sizeof(u32), c1, c2);
 
-	seed_checksum = rtc_read8(CMOS_OFFSET_MRC_SEED_CHK);
-	seed_checksum |= rtc_read8(CMOS_OFFSET_MRC_SEED_CHK + 1) << 8;
+	seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK);
+	seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8;
 
 	if (checksum != seed_checksum) {
 		debug("%s: invalid seed checksum\n", __func__);
@@ -223,13 +231,21 @@ static int build_mrc_data(struct mrc_data_container **datap)
 static int write_seeds_to_cmos(struct pei_data *pei_data)
 {
 	u16 c1, c2, checksum;
+	struct udevice *dev;
+	int rcode = 0;
+
+	rcode = uclass_get_device(UCLASS_RTC, 0, &dev);
+	if (rcode) {
+		debug("Cannot find RTC: err=%d\n", rcode);
+		return -ENODEV;
+	}
 
 	/* Save the MRC seed values to CMOS */
-	rtc_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
+	rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
 	debug("Save scrambler seed    0x%08x to CMOS 0x%02x\n",
 	      pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
 
-	rtc_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
+	rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
 	debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
 	      pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
 
@@ -240,8 +256,8 @@ static int write_seeds_to_cmos(struct pei_data *pei_data)
 				 sizeof(u32));
 	checksum = add_ip_checksums(sizeof(u32), c1, c2);
 
-	rtc_write8(CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff);
-	rtc_write8(CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff);
+	rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff);
+	rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff);
 
 	return 0;
 }

arch/x86/dts/chromebook_link.dts

@@ -2,6 +2,7 @@
 
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
+/include/ "rtc.dtsi"
 
 / {
 	model = "Google Link";

arch/x86/dts/chromebox_panther.dts

@@ -2,6 +2,7 @@
 
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
+/include/ "rtc.dtsi"
 
 / {
 	model = "Google Panther";

arch/x86/dts/galileo.dts

@@ -10,6 +10,7 @@
 #include <dt-bindings/interrupt-router/intel-irq.h>
 
 /include/ "skeleton.dtsi"
+/include/ "rtc.dtsi"
 
 / {
 	model = "Intel Galileo";

arch/x86/dts/minnowmax.dts

@@ -10,6 +10,7 @@
 
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
+/include/ "rtc.dtsi"
 
 / {
 	model = "Intel Minnowboard Max";

arch/x86/dts/qemu-x86_i440fx.dts

@@ -10,6 +10,7 @@
 
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
+/include/ "rtc.dtsi"
 
 / {
 	model = "QEMU x86 (I440FX)";

arch/x86/dts/qemu-x86_q35.dts

@@ -20,6 +20,7 @@
 
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
+/include/ "rtc.dtsi"
 
 / {
 	model = "QEMU x86 (Q35)";

arch/x86/dts/rtc.dtsi

@@ -1,6 +1,7 @@
 / {
 	rtc {
 		compatible = "motorola,mc146818";
+		u-boot,dm-pre-reloc;
 		reg = <0x70 2>;
 	};
 };

configs/chromebook_link_defconfig

@@ -17,5 +17,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_DM_RTC=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_SYS_VSNPRINTF=y

configs/chromebox_panther_defconfig

@@ -17,5 +17,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_DM_RTC=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_SYS_VSNPRINTF=y

configs/galileo_defconfig

@@ -15,5 +15,6 @@ CONFIG_SPL_DISABLE_OF_CONTROL=y
 CONFIG_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_RTC=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_SYS_VSNPRINTF=y

configs/minnowmax_defconfig

@@ -21,5 +21,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_DM_RTC=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_SYS_VSNPRINTF=y

configs/qemu-x86_defconfig

@@ -13,5 +13,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_111=y
+CONFIG_DM_RTC=y
 CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_SYS_VSNPRINTF=y