arm: socfpga: clock: Clean up pll_config.h

Extract the clock configuration horribleness caused by pll_config.h in
the following manner.

First of all, introduce a few new accessors which return values of
various clocks used in clock_manager.c and use them in clock_manager.c .
These accessors replace those few macros which came from pll_config.h
originally. Also introduce an accessor which returns the struct cm_config
default configuration for the clock manager used in SPL.

The accessors are implemented in a board-specific wrap_pll_config.c
file, whose sole purpose is to include the qts-generated pll_config.h
and provide only the necessary values to the clock manager.

The purpose of this design is to limit the scope of inclusion for the
pll_config.h , which thus far was included build-wide and poluted the
namespace. With this change, the inclusion is limited to just the new
wrap_pll_config.c file, which in turn provides three simple functions
for the clock_manager.c to use.

Signed-off-by: Marek Vasut <marex@denx.de>

arch/arm/mach-socfpga/clock_manager.c

@@ -88,7 +88,7 @@ static void cm_write_with_phase(uint32_t value,
  * Ungate clocks
  */
 
-void cm_basic_init(const struct cm_config *cfg)
+void cm_basic_init(const struct cm_config * const cfg)
 {
 	uint32_t start, timeout;
 
@@ -336,7 +336,7 @@ static unsigned int cm_get_main_vco_clk_hz(void)
 
 	/* get the main VCO clock */
 	reg = readl(&clock_manager_base->main_pll.vco);
-	clock = CONFIG_HPS_CLK_OSC1_HZ;
+	clock = cm_get_osc_clk_hz(1);
 	clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
 		  CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
 	clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
@@ -354,11 +354,11 @@ static unsigned int cm_get_per_vco_clk_hz(void)
 	reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
 	      CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
 	if (reg == CLKMGR_VCO_SSRC_EOSC1)
-		clock = CONFIG_HPS_CLK_OSC1_HZ;
+		clock = cm_get_osc_clk_hz(1);
 	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
-		clock = CONFIG_HPS_CLK_OSC2_HZ;
+		clock = cm_get_osc_clk_hz(2);
 	else if (reg == CLKMGR_VCO_SSRC_F2S)
-		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+		clock = cm_get_f2s_per_ref_clk_hz();
 
 	/* get the PER VCO clock */
 	reg = readl(&clock_manager_base->per_pll.vco);
@@ -393,11 +393,11 @@ unsigned long cm_get_sdram_clk_hz(void)
 	reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
 	      CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
 	if (reg == CLKMGR_VCO_SSRC_EOSC1)
-		clock = CONFIG_HPS_CLK_OSC1_HZ;
+		clock = cm_get_osc_clk_hz(1);
 	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
-		clock = CONFIG_HPS_CLK_OSC2_HZ;
+		clock = cm_get_osc_clk_hz(2);
 	else if (reg == CLKMGR_VCO_SSRC_F2S)
-		clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+		clock = cm_get_f2s_sdr_ref_clk_hz();
 
 	/* get the SDRAM VCO clock */
 	reg = readl(&clock_manager_base->sdr_pll.vco);
@@ -459,7 +459,7 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
 	      CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
 
 	if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
-		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+		clock = cm_get_f2s_per_ref_clk_hz();
 	} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
 		clock = cm_get_main_vco_clk_hz();
 
@@ -489,7 +489,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
 	      CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
 
 	if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
-		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+		clock = cm_get_f2s_per_ref_clk_hz();
 	} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
 		clock = cm_get_main_vco_clk_hz();
 
@@ -524,10 +524,10 @@ static void cm_print_clock_quick_summary(void)
 {
 	printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
 	printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
-	printf("EOSC1       %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000);
-	printf("EOSC2       %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000);
-	printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000);
-	printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000);
+	printf("EOSC1       %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
+	printf("EOSC2       %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
+	printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
+	printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
 	printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
 	printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
 	printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);

arch/arm/mach-socfpga/include/mach/clock_manager.h

@@ -15,6 +15,12 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 unsigned int cm_get_mmc_controller_clk_hz(void);
 unsigned int cm_get_qspi_controller_clk_hz(void);
 unsigned int cm_get_spi_controller_clk_hz(void);
+const unsigned int cm_get_osc_clk_hz(const int osc);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
 #endif
 
 struct cm_config {
@@ -51,7 +57,7 @@ struct cm_config {
 	uint32_t s2fuser2clk;
 };
 
-extern void cm_basic_init(const struct cm_config *cfg);
+void cm_basic_init(const struct cm_config * const cfg);
 
 struct socfpga_clock_manager_main_pll {
 	u32	vco;

arch/arm/mach-socfpga/spl.c

@@ -23,31 +23,6 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 
-#define MAIN_VCO_BASE (					\
-	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
-		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\
-		CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)	\
-	)
-
-#define PERI_VCO_BASE (					\
-	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\
-		CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\
-	(CONFIG_HPS_PERPLLGRP_VCO_DENOM <<		\
-		CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<		\
-		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\
-	)
-
-#define SDR_VCO_BASE (					\
-	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\
-		CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\
-	(CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<		\
-		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	\
-	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\
-		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
-	)
-
 void board_init_f(ulong dummy)
 {
 	struct socfpga_system_manager *sysmgr_regs =
@@ -85,91 +60,8 @@ void spl_board_init(void)
 {
 	unsigned long sdram_size;
 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
-	struct cm_config cm_default_cfg = {
-		/* main group */
-		MAIN_VCO_BASE,
-		(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
-			CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
-			CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
-			CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
-			CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
-			CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
-			CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
-			CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
-		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
-			CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
-		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
-			CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
-		(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
-			CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
-			CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
-		(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
-			CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
-			CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
-		(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
-			CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
-		(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
-			CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
-
-		/* peripheral group */
-		PERI_VCO_BASE,
-		(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
-			CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
-			CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
-			CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
-			CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
-			CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
-			CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
-			CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
-		(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
-			CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
-		(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
-			CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
-		(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
-			CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
-			CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
-		(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
-			CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
-		(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
-			CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
-		(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
-			CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
-
-		/* sdram pll group */
-		SDR_VCO_BASE,
-		(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
-			CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
-		(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
-			CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
-		(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
-			CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
-		(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
-			CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
-		(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
-			CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
-		(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
-			CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
-		(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
-			CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
-		(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
-			CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
-
-	};
+	const struct cm_config *cm_default_cfg = cm_get_default_config();
+#endif
 
 	debug("Freezing all I/O banks\n");
 	/* freeze all IO banks */
@@ -183,7 +75,7 @@ void spl_board_init(void)
 
 	debug("Reconfigure Clock Manager\n");
 	/* reconfigure the PLLs */
-	cm_basic_init(&cm_default_cfg);
+	cm_basic_init(cm_default_cfg);
 
 	/* Enable bootrom to configure IOs. */
 	sysmgr_enable_warmrstcfgio();

board/altera/socfpga/Makefile

@@ -6,5 +6,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	:= socfpga.o
+obj-y	:= socfpga.o wrap_pll_config.o
 obj-$(CONFIG_SPL_BUILD) += qts/

board/altera/socfpga/wrap_pll_config.c

@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include "qts/pll_config.h"
+
+#define MAIN_VCO_BASE (					\
+	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
+		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_MAINPLLGRP_VCO_NUMER <<		\
+		CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
+#define PERI_VCO_BASE (					\
+	(CONFIG_HPS_PERPLLGRP_VCO_PSRC <<		\
+		CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) |	\
+	(CONFIG_HPS_PERPLLGRP_VCO_DENOM <<		\
+		CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_PERPLLGRP_VCO_NUMER <<		\
+		CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
+#define SDR_VCO_BASE (					\
+	(CONFIG_HPS_SDRPLLGRP_VCO_SSRC <<		\
+		CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) |	\
+	(CONFIG_HPS_SDRPLLGRP_VCO_DENOM <<		\
+		CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) |	\
+	(CONFIG_HPS_SDRPLLGRP_VCO_NUMER <<		\
+		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
+	)
+
+static const struct cm_config cm_default_cfg = {
+	/* main group */
+	MAIN_VCO_BASE,
+	(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
+		CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
+		CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
+		CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
+		CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
+		CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
+		CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
+		CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
+		CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
+		CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
+		CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
+		CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
+		CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
+	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
+		CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
+	(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
+		CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
+
+	/* peripheral group */
+	PERI_VCO_BASE,
+	(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
+		CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
+		CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
+		CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
+		CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
+		CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
+		CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
+		CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
+		CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
+		CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
+		CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
+		CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
+	(CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
+		CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_SRC_NAND <<
+		CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
+	(CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
+		CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
+
+	/* sdram pll group */
+	SDR_VCO_BASE,
+	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
+	(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
+		CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
+	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
+	(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
+		CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
+	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
+		CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
+	(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
+		CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
+	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
+	(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
+		CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
+};
+
+const struct cm_config * const cm_get_default_config(void)
+{
+	return &cm_default_cfg;
+}
+
+const unsigned int cm_get_osc_clk_hz(const int osc)
+{
+	if (osc == 1)
+		return CONFIG_HPS_CLK_OSC1_HZ;
+	else if (osc == 2)
+		return CONFIG_HPS_CLK_OSC2_HZ;
+	else
+		return 0;
+}
+
+const unsigned int cm_get_f2s_per_ref_clk_hz(void)
+{
+	return CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+}
+
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
+{
+	return CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+}

include/configs/socfpga_arria5.h

@@ -9,7 +9,6 @@
 #include <asm/arch/socfpga_base_addrs.h>
 #include "../../board/altera/socfpga/qts/pinmux_config.h"
 #include "../../board/altera/socfpga/qts/iocsr_config.h"
-#include "../../board/altera/socfpga/qts/pll_config.h"
 
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH

include/configs/socfpga_cyclone5.h

@@ -9,7 +9,6 @@
 #include <asm/arch/socfpga_base_addrs.h>
 #include "../../board/altera/socfpga/qts/pinmux_config.h"
 #include "../../board/altera/socfpga/qts/iocsr_config.h"
-#include "../../board/altera/socfpga/qts/pll_config.h"
 
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH