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@@ -156,7 +156,9 @@ int board_init(void)
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{
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{
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char *env_hwconfig;
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char *env_hwconfig;
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u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
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u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
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+#ifdef CONFIG_FSL_MC_ENET
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u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
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u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
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+#endif
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u32 val;
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u32 val;
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init_final_memctl_regs();
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init_final_memctl_regs();
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@@ -178,8 +180,10 @@ int board_init(void)
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QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
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QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
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+#ifdef CONFIG_FSL_MC_ENET
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/* invert AQR405 IRQ pins polarity */
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/* invert AQR405 IRQ pins polarity */
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out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
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out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
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+#endif
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return 0;
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return 0;
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}
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}
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@@ -261,7 +265,9 @@ void fdt_fixup_board_enet(void *fdt)
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#ifdef CONFIG_OF_BOARD_SETUP
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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{
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+#ifdef CONFIG_FSL_MC_ENET
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int err;
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int err;
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+#endif
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u64 base[CONFIG_NR_DRAM_BANKS];
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u64 base[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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