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@@ -73,18 +73,41 @@
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>;
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>;
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st,pkcs = <
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st,pkcs = <
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- CLK_CKPER_DISABLED
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+ CLK_CKPER_HSE
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+ CLK_FMC_ACLK
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+ CLK_QSPI_ACLK
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+ CLK_ETH_DISABLED
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CLK_SDMMC12_PLL3R
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CLK_SDMMC12_PLL3R
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+ CLK_DSI_DSIPLL
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CLK_STGEN_HSE
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CLK_STGEN_HSE
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- CLK_I2C46_PCLK5
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- CLK_I2C12_PCLK1
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+ CLK_USBPHY_HSE
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+ CLK_SPI2S1_PLL3Q
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+ CLK_SPI2S23_PLL3Q
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+ CLK_SPI45_HSI
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+ CLK_SPI6_HSI
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+ CLK_I2C46_HSI
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CLK_SDMMC3_PLL3R
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CLK_SDMMC3_PLL3R
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- CLK_I2C35_PCLK1
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- CLK_UART1_PCLK5
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- CLK_UART24_PCLK1
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- CLK_UART35_PCLK1
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- CLK_UART6_PCLK2
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- CLK_UART78_PCLK1
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+ CLK_USBO_USBPHY
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+ CLK_ADC_CKPER
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+ CLK_CEC_LSE
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+ CLK_I2C12_HSI
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+ CLK_I2C35_HSI
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+ CLK_UART1_HSI
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+ CLK_UART24_HSI
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+ CLK_UART35_HSI
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+ CLK_UART6_HSI
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+ CLK_UART78_HSI
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+ CLK_SPDIF_PLL3Q
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+ CLK_FDCAN_PLL4Q
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+ CLK_SAI1_PLL3Q
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+ CLK_SAI2_PLL3Q
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+ CLK_SAI3_PLL3Q
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+ CLK_SAI4_PLL3Q
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+ CLK_RNG1_CSI
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+ CLK_RNG2_CSI
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+ CLK_LPTIM1_PCLK1
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+ CLK_LPTIM23_PCLK3
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+ CLK_LPTIM45_PCLK3
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>;
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>;
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/* VCO = 1300.0 MHz => P = 650 (CPU) */
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/* VCO = 1300.0 MHz => P = 650 (CPU) */
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@@ -101,9 +124,10 @@
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u-boot,dm-pre-reloc;
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u-boot,dm-pre-reloc;
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};
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};
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- /* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */
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+ /* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */
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pll3: st,pll@2 {
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pll3: st,pll@2 {
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- cfg = < 3 128 3 20 7 PQR(1,1,1) >;
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+ cfg = < 2 97 3 15 7 PQR(1,1,1) >;
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+ frac = < 0x9ba >;
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u-boot,dm-pre-reloc;
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u-boot,dm-pre-reloc;
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};
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};
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Patrick Delaunay