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+/*
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+ * Copyright (C) 2015 Compulab, Ltd.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#include <common.h>
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+#include <i2c.h>
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+#include <miiphy.h>
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+#include <cpsw.h>
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+#include <spl.h>
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+#include <asm/arch/clock.h>
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+#include <asm/arch/sys_proto.h>
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+#include <asm/arch/mux.h>
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+#include <asm/arch/ddr_defs.h>
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+#include <asm/errno.h>
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+#include <asm/gpio.h>
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+#include <asm/emif.h>
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+#include <power/pmic.h>
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+#include <power/tps65218.h>
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+#include "board.h"
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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+
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+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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+
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+const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 };
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+const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 };
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+const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 };
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+const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 };
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+
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+const struct ctrl_ioregs ioregs_ddr3 = {
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+ .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
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+ .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
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+ .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
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+ .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
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+ .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
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+ .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
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+ .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
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+ .emif_sdram_config_ext = 0x0143,
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+};
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+
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+/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
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+struct emif_regs ddr3_emif_regs = {
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+ .sdram_config = 0x638413B2,
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+ .ref_ctrl = 0x00000C30,
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+ .sdram_tim1 = 0xEAAAD4DB,
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+ .sdram_tim2 = 0x266B7FDA,
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+ .sdram_tim3 = 0x107F8678,
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+ .read_idle_ctrl = 0x00050000,
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+ .zq_config = 0x50074BE4,
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+ .temp_alert_config = 0x0,
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+ .emif_ddr_phy_ctlr_1 = 0x0E004008,
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+ .emif_ddr_ext_phy_ctrl_1 = 0x08020080,
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+ .emif_ddr_ext_phy_ctrl_2 = 0x00000066,
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+ .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
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+ .emif_ddr_ext_phy_ctrl_4 = 0x000000B9,
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+ .emif_ddr_ext_phy_ctrl_5 = 0x000000E6,
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+ .emif_rd_wr_exec_thresh = 0x80000405,
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+ .emif_prio_class_serv_map = 0x80000001,
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+ .emif_connect_id_serv_1_map = 0x80000094,
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+ .emif_connect_id_serv_2_map = 0x00000000,
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+ .emif_cos_config = 0x000FFFFF
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+};
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+
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+const u32 ext_phy_ctrl_const_base_ddr3[] = {
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+ 0x00000000,
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+ 0x00000044,
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+ 0x00000044,
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+ 0x00000046,
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+ 0x00000046,
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+ 0x00000000,
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+ 0x00000059,
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+ 0x00000077,
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+ 0x00000093,
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+ 0x000000A8,
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+ 0x00000000,
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+ 0x00000019,
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+ 0x00000037,
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+ 0x00000053,
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+ 0x00000068,
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+ 0x00000000,
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+ 0x0,
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+ 0x0,
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+ 0x40000000,
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+ 0x08102040
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+};
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+
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+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
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+{
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+ *regs = ext_phy_ctrl_const_base_ddr3;
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+ *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
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+}
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+
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+const struct dpll_params *get_dpll_ddr_params(void)
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+{
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+ return &dpll_ddr;
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+}
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+
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+const struct dpll_params *get_dpll_mpu_params(void)
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+{
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+ return &dpll_mpu;
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+}
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+
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+const struct dpll_params *get_dpll_core_params(void)
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+{
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+ return &dpll_core;
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+}
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+
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+const struct dpll_params *get_dpll_per_params(void)
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+{
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+ return &dpll_per;
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+}
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+
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+static void enable_vtt_regulator(void)
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+{
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+ u32 temp;
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+
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+ writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
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+ writel(GPIO_SETDATAOUT(7), AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
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+ temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
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+ temp = temp & ~(GPIO_OE_ENABLE(7));
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+ writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
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+}
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+
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+void sdram_init(void)
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+{
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+ unsigned long ram_size;
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+
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+ enable_vtt_regulator();
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+ config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
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+ ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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+ if (ram_size == 0x80000000 ||
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+ ram_size == 0x40000000 ||
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+ ram_size == 0x20000000)
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+ return;
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+
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+ ddr3_emif_regs.sdram_config = 0x638453B2;
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+ config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
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+ ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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+ if (ram_size == 0x08000000)
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+ return;
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+
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+ hang();
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+}
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+#endif
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+
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+/* setup board specific PMIC */
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+int power_init_board(void)
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+{
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+ struct pmic *p;
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+
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+ power_tps65218_init(I2C_PMIC);
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+ p = pmic_get("TPS65218_PMIC");
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+ if (p && !pmic_probe(p))
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+ puts("PMIC: TPS65218\n");
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+
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+ return 0;
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+}
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+
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+int board_init(void)
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+{
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+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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+ gpmc_init();
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+ set_i2c_pin_mux();
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+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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+ i2c_probe(TPS65218_CHIP_PM);
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_DRIVER_TI_CPSW
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+
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+static void cpsw_control(int enabled)
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+{
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+ return;
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+}
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+
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+static struct cpsw_slave_data cpsw_slaves[] = {
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+ {
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+ .slave_reg_ofs = 0x208,
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+ .sliver_reg_ofs = 0xd80,
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+ .phy_addr = 0,
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+ .phy_if = PHY_INTERFACE_MODE_RGMII,
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+ },
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+ {
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+ .slave_reg_ofs = 0x308,
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+ .sliver_reg_ofs = 0xdc0,
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+ .phy_addr = 1,
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+ .phy_if = PHY_INTERFACE_MODE_RGMII,
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+ },
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+};
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+
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+static struct cpsw_platform_data cpsw_data = {
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+ .mdio_base = CPSW_MDIO_BASE,
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+ .cpsw_base = CPSW_BASE,
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+ .mdio_div = 0xff,
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+ .channels = 8,
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+ .cpdma_reg_ofs = 0x800,
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+ .slaves = 2,
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+ .slave_data = cpsw_slaves,
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+ .ale_reg_ofs = 0xd00,
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+ .ale_entries = 1024,
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+ .host_port_reg_ofs = 0x108,
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+ .hw_stats_reg_ofs = 0x900,
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+ .bd_ram_ofs = 0x2000,
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+ .mac_control = (1 << 5),
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+ .control = cpsw_control,
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+ .host_port_num = 0,
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+ .version = CPSW_CTRL_VERSION_2,
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+};
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+
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+#define GPIO_PHY1_RST 170
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+#define GPIO_PHY2_RST 168
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+
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+int board_phy_config(struct phy_device *phydev)
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+{
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+ unsigned short val;
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+
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+ /* introduce tx clock delay */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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+ val |= 0x0100;
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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+
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+ if (phydev->drv->config)
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+ return phydev->drv->config(phydev);
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+
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+ return 0;
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+}
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+
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+static void board_phy_init(void)
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+{
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+ set_mdio_pin_mux();
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+ writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */
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+ writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */
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+ writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */
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+
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+ /* For revision A */
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+ writel(0x2000009, 0x44df2e6c);
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+ writel(0x38a, 0x44df2e70);
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+
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+ mdelay(10);
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+
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+ gpio_request(GPIO_PHY1_RST, "phy1_rst");
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+ gpio_request(GPIO_PHY2_RST, "phy2_rst");
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+ gpio_direction_output(GPIO_PHY1_RST, 0);
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+ gpio_direction_output(GPIO_PHY2_RST, 0);
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+ mdelay(2);
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+
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+ gpio_set_value(GPIO_PHY1_RST, 1);
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+ gpio_set_value(GPIO_PHY2_RST, 1);
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+ mdelay(2);
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+}
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+
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+int board_eth_init(bd_t *bis)
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+{
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+ int rv;
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+
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+ set_rgmii_pin_mux();
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+ writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
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+ board_phy_init();
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+
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+ rv = cpsw_register(&cpsw_data);
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+ if (rv < 0)
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+ printf("Error %d registering CPSW switch\n", rv);
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+
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+ return rv;
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+}
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+#endif
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Nikita Kiryanov