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-/*
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- * Copyright (C) 2005 Sandburst Corporation
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- *
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- * See file CREDITS for list of people who contributed to this
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- * project.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License as
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- * published by the Free Software Foundation; either version 2 of
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- * the License, or (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, write to the Free Software
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- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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- * MA 02111-1307 USA
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- */
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-
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-/*
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- * Ported from arch/powerpc/cpu/ppc4xx/i2c.c by AS HARNOIS by
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- * Travis B. Sawyer
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- * Sandburst Corporation.
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- */
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-#include <common.h>
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-#include <asm/ppc4xx.h>
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-#include <asm/ppc4xx-i2c.h>
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-#include <i2c.h>
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-#include <command.h>
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-#include "ppc440gx_i2c.h"
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-#include <asm/io.h>
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-
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-#ifdef CONFIG_I2C_BUS1
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-
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-#define IIC_OK 0
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-#define IIC_NOK 1
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-#define IIC_NOK_LA 2 /* Lost arbitration */
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-#define IIC_NOK_ICT 3 /* Incomplete transfer */
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-#define IIC_NOK_XFRA 4 /* Transfer aborted */
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-#define IIC_NOK_DATA 5 /* No data in buffer */
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-#define IIC_NOK_TOUT 6 /* Transfer timeout */
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-
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-#define IIC_TIMEOUT 1 /* 1 second */
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-#if defined(CONFIG_SYS_I2C_NOPROBES)
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-static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
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-#endif
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-
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-static struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_REGISTERS_BUS1_BASE_ADDRESS;
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-
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-static void _i2c_bus1_reset (void)
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-{
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- int i, status;
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-
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- /* Reset status register */
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- /* write 1 in SCMP and IRQA to clear these fields */
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- out_8 (IIC_STS1, 0x0A);
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-
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- /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
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- out_8 (IIC_EXTSTS1, 0x8F);
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- __asm__ volatile ("eieio");
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-
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- /*
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- * Get current state, reset bus
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- * only if no transfers are pending.
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- */
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- i = 10;
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- do {
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- /* Get status */
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- status = in_8 (IIC_STS1);
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- udelay (500); /* 500us */
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- i--;
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- } while ((status & IIC_STS_PT) && (i > 0));
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- /* Soft reset controller */
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- status = in_8 (IIC_XTCNTLSS1);
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- out_8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST));
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- __asm__ volatile ("eieio");
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-
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- /* make sure where in initial state, data hi, clock hi */
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- out_8 (IIC_DIRECTCNTL1, 0xC);
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- for (i = 0; i < 10; i++) {
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- if ((in_8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) {
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- /* clock until we get to known state */
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- out_8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */
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- udelay (100); /* 100us */
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- out_8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */
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- udelay (100); /* 100us */
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- } else {
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- break;
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- }
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- }
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- /* send start condition */
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- out_8 (IIC_DIRECTCNTL1, 0x4);
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- udelay (1000); /* 1ms */
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- /* send stop condition */
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- out_8 (IIC_DIRECTCNTL1, 0xC);
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- udelay (1000); /* 1ms */
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- /* Unreset controller */
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- out_8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST));
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- udelay (1000); /* 1ms */
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-}
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-
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-void i2c1_init (int speed, int slaveadd)
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-{
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- sys_info_t sysInfo;
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- unsigned long freqOPB;
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- int val, divisor;
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-
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-#ifdef CONFIG_SYS_I2C_INIT_BOARD
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- /* call board specific i2c bus reset routine before accessing the */
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- /* environment, which might be in a chip on that bus. For details */
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- /* about this problem see doc/I2C_Edge_Conditions. */
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- i2c_init_board();
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-#endif
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-
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- /* Handle possible failed I2C state */
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- /* FIXME: put this into i2c_init_board()? */
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- _i2c_bus1_reset ();
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-
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- /* clear lo master address */
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- out_8 (IIC_LMADR1, 0);
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-
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- /* clear hi master address */
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- out_8 (IIC_HMADR1, 0);
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-
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- /* clear lo slave address */
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- out_8 (IIC_LSADR1, 0);
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-
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- /* clear hi slave address */
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- out_8 (IIC_HSADR1, 0);
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-
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- /* Clock divide Register */
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- /* get OPB frequency */
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- get_sys_info (&sysInfo);
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- freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
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- /* set divisor according to freqOPB */
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- divisor = (freqOPB - 1) / 10000000;
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- if (divisor == 0)
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- divisor = 1;
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- out_8 (IIC_CLKDIV1, divisor);
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-
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- /* no interrupts */
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- out_8 (IIC_INTRMSK1, 0);
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-
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- /* clear transfer count */
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- out_8 (IIC_XFRCNT1, 0);
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-
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- /* clear extended control & stat */
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- /* write 1 in SRC SRS SWC SWS to clear these fields */
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- out_8 (IIC_XTCNTLSS1, 0xF0);
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-
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- /* Mode Control Register
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- Flush Slave/Master data buffer */
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- out_8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
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- __asm__ volatile ("eieio");
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-
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-
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- val = in_8(IIC_MDCNTL1);
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- __asm__ volatile ("eieio");
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-
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- /* Ignore General Call, slave transfers are ignored,
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- disable interrupts, exit unknown bus state, enable hold
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- SCL
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- 100kHz normaly or FastMode for 400kHz and above
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- */
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-
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- val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
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- if( speed >= 400000 ){
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- val |= IIC_MDCNTL_FSM;
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- }
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- out_8 (IIC_MDCNTL1, val);
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-
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- /* clear control reg */
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- out_8 (IIC_CNTL1, 0x00);
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- __asm__ volatile ("eieio");
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-
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-}
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-
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-/*
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- This code tries to use the features of the 405GP i2c
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- controller. It will transfer up to 4 bytes in one pass
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- on the loop. It only does out_8(lbz) to the buffer when it
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- is possible to do out16(lhz) transfers.
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-
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- cmd_type is 0 for write 1 for read.
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-
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- addr_len can take any value from 0-255, it is only limited
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- by the char, we could make it larger if needed. If it is
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- 0 we skip the address write cycle.
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-
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- Typical case is a Write of an addr followd by a Read. The
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- IBM FAQ does not cover this. On the last byte of the write
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- we don't set the creg CHT bit, and on the first bytes of the
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- read we set the RPST bit.
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-
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- It does not support address only transfers, there must be
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- a data part. If you want to write the address yourself, put
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- it in the data pointer.
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-
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- It does not support transfer to/from address 0.
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-
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- It does not check XFRCNT.
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-*/
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-static
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-int i2c_transfer1(unsigned char cmd_type,
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- unsigned char chip,
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- unsigned char addr[],
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- unsigned char addr_len,
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- unsigned char data[],
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- unsigned short data_len )
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-{
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- unsigned char* ptr;
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- int reading;
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- int tran,cnt;
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- int result;
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- int status;
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- int i;
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- uchar creg;
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-
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- if( data == 0 || data_len == 0 ){
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- /*Don't support data transfer of no length or to address 0*/
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- printf( "i2c_transfer: bad call\n" );
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- return IIC_NOK;
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- }
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- if( addr && addr_len ){
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- ptr = addr;
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- cnt = addr_len;
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- reading = 0;
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- }else{
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- ptr = data;
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- cnt = data_len;
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- reading = cmd_type;
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- }
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-
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- /*Clear Stop Complete Bit*/
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- out_8(IIC_STS1,IIC_STS_SCMP);
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- /* Check init */
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- i=10;
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- do {
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- /* Get status */
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- status = in_8(IIC_STS1);
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- __asm__ volatile("eieio");
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- i--;
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- } while ((status & IIC_STS_PT) && (i>0));
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-
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- if (status & IIC_STS_PT) {
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- result = IIC_NOK_TOUT;
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- return(result);
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- }
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- /*flush the Master/Slave Databuffers*/
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- out_8(IIC_MDCNTL1, ((in_8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
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- /*need to wait 4 OPB clocks? code below should take that long*/
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-
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- /* 7-bit adressing */
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- out_8(IIC_HMADR1,0);
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- out_8(IIC_LMADR1, chip);
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- __asm__ volatile("eieio");
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-
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- tran = 0;
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- result = IIC_OK;
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- creg = 0;
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-
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- while ( tran != cnt && (result == IIC_OK)) {
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- int bc,j;
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-
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- /* Control register =
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- Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
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- Transfer is a sequence of transfers
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- */
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- creg |= IIC_CNTL_PT;
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-
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- bc = (cnt - tran) > 4 ? 4 :
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- cnt - tran;
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- creg |= (bc-1)<<4;
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- /* if the real cmd type is write continue trans*/
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- if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
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- creg |= IIC_CNTL_CHT;
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-
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- if (reading)
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- creg |= IIC_CNTL_READ;
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- else {
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- for(j=0; j<bc; j++) {
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- /* Set buffer */
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- out_8(IIC_MDBUF1,ptr[tran+j]);
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- __asm__ volatile("eieio");
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- }
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- }
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- out_8(IIC_CNTL1, creg );
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- __asm__ volatile("eieio");
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-
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- /* Transfer is in progress
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- we have to wait for upto 5 bytes of data
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- 1 byte chip address+r/w bit then bc bytes
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- of data.
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- udelay(10) is 1 bit time at 100khz
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- Doubled for slop. 20 is too small.
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- */
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- i=2*5*8;
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- do {
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- /* Get status */
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- status = in_8(IIC_STS1);
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- __asm__ volatile("eieio");
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- udelay (10);
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- i--;
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- } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
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- && (i>0));
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-
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- if (status & IIC_STS_ERR) {
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- result = IIC_NOK;
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- status = in_8 (IIC_EXTSTS1);
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- /* Lost arbitration? */
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- if (status & IIC_EXTSTS_LA)
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- result = IIC_NOK_LA;
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- /* Incomplete transfer? */
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- if (status & IIC_EXTSTS_ICT)
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- result = IIC_NOK_ICT;
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- /* Transfer aborted? */
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- if (status & IIC_EXTSTS_XFRA)
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- result = IIC_NOK_XFRA;
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- } else if ( status & IIC_STS_PT) {
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- result = IIC_NOK_TOUT;
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- }
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- /* Command is reading => get buffer */
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- if ((reading) && (result == IIC_OK)) {
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- /* Are there data in buffer */
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- if (status & IIC_STS_MDBS) {
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- /*
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- even if we have data we have to wait 4OPB clocks
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- for it to hit the front of the FIFO, after that
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- we can just read. We should check XFCNT here and
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- if the FIFO is full there is no need to wait.
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- */
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- udelay (1);
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- for(j=0;j<bc;j++) {
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- ptr[tran+j] = in_8(IIC_MDBUF1);
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- __asm__ volatile("eieio");
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- }
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- } else
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- result = IIC_NOK_DATA;
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- }
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- creg = 0;
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- tran+=bc;
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- if( ptr == addr && tran == cnt ) {
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- ptr = data;
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- cnt = data_len;
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- tran = 0;
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- reading = cmd_type;
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- if( reading )
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- creg = IIC_CNTL_RPST;
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- }
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- }
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- return (result);
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-}
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-
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-int i2c_probe1 (uchar chip)
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-{
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- uchar buf[1];
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-
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- buf[0] = 0;
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-
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- /*
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- * What is needed is to send the chip address and verify that the
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- * address was <ACK>ed (i.e. there was a chip at that address which
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- * drove the data line low).
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- */
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- return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0);
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-}
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-
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-
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-int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
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-{
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- uchar xaddr[4];
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- int ret;
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-
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- if ( alen > 4 ) {
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- printf ("I2C read: addr len %d not supported\n", alen);
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- return 1;
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- }
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-
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- if ( alen > 0 ) {
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- xaddr[0] = (addr >> 24) & 0xFF;
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- xaddr[1] = (addr >> 16) & 0xFF;
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- xaddr[2] = (addr >> 8) & 0xFF;
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- xaddr[3] = addr & 0xFF;
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- }
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-
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-
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-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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- /*
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- * EEPROM chips that implement "address overflow" are ones
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- * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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- * address and the extra bits end up in the "chip address"
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- * bit slots. This makes a 24WC08 (1Kbyte) chip look like
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- * four 256 byte chips.
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- *
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- * Note that we consider the length of the address field to
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- * still be one byte because the extra address bits are
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- * hidden in the chip address.
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- */
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- if( alen > 0 )
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- chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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-#endif
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- if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
|
|
|
- printf( "I2c read: failed %d\n", ret);
|
|
|
- return 1;
|
|
|
- }
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len)
|
|
|
-{
|
|
|
- uchar xaddr[4];
|
|
|
-
|
|
|
- if ( alen > 4 ) {
|
|
|
- printf ("I2C write: addr len %d not supported\n", alen);
|
|
|
- return 1;
|
|
|
-
|
|
|
- }
|
|
|
- if ( alen > 0 ) {
|
|
|
- xaddr[0] = (addr >> 24) & 0xFF;
|
|
|
- xaddr[1] = (addr >> 16) & 0xFF;
|
|
|
- xaddr[2] = (addr >> 8) & 0xFF;
|
|
|
- xaddr[3] = addr & 0xFF;
|
|
|
- }
|
|
|
-
|
|
|
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
|
|
- /*
|
|
|
- * EEPROM chips that implement "address overflow" are ones
|
|
|
- * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
|
|
- * address and the extra bits end up in the "chip address"
|
|
|
- * bit slots. This makes a 24WC08 (1Kbyte) chip look like
|
|
|
- * four 256 byte chips.
|
|
|
- *
|
|
|
- * Note that we consider the length of the address field to
|
|
|
- * still be one byte because the extra address bits are
|
|
|
- * hidden in the chip address.
|
|
|
- */
|
|
|
- if( alen > 0 )
|
|
|
- chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
|
|
|
-#endif
|
|
|
-
|
|
|
- return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
|
|
|
-}
|
|
|
-
|
|
|
-/*-----------------------------------------------------------------------
|
|
|
- * Read a register
|
|
|
- */
|
|
|
-uchar i2c_reg_read1(uchar i2c_addr, uchar reg)
|
|
|
-{
|
|
|
- uchar buf;
|
|
|
-
|
|
|
- i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1);
|
|
|
-
|
|
|
- return(buf);
|
|
|
-}
|
|
|
-
|
|
|
-/*-----------------------------------------------------------------------
|
|
|
- * Write a register
|
|
|
- */
|
|
|
-void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val)
|
|
|
-{
|
|
|
- i2c_write1(i2c_addr, reg, 1, &val, 1);
|
|
|
-}
|
|
|
-
|
|
|
-
|
|
|
-int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|
|
-{
|
|
|
- int j;
|
|
|
-#if defined(CONFIG_SYS_I2C_NOPROBES)
|
|
|
- int k, skip;
|
|
|
-#endif
|
|
|
-
|
|
|
- puts ("Valid chip addresses:");
|
|
|
- for(j = 0; j < 128; j++) {
|
|
|
-#if defined(CONFIG_SYS_I2C_NOPROBES)
|
|
|
- skip = 0;
|
|
|
- for (k = 0; k < sizeof(i2c_no_probes); k++){
|
|
|
- if (j == i2c_no_probes[k]){
|
|
|
- skip = 1;
|
|
|
- break;
|
|
|
- }
|
|
|
- }
|
|
|
- if (skip)
|
|
|
- continue;
|
|
|
-#endif
|
|
|
- if(i2c_probe1(j) == 0) {
|
|
|
- printf(" %02X", j);
|
|
|
- }
|
|
|
- }
|
|
|
- putc ('\n');
|
|
|
-
|
|
|
-#if defined(CONFIG_SYS_I2C_NOPROBES)
|
|
|
- puts ("Excluded chip addresses:");
|
|
|
- for( k = 0; k < sizeof(i2c_no_probes); k++ )
|
|
|
- printf(" %02X", i2c_no_probes[k] );
|
|
|
- putc ('\n');
|
|
|
-#endif
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-U_BOOT_CMD(
|
|
|
- iprobe1, 1, 1, do_i2c1_probe,
|
|
|
- "probe to discover valid I2C chip addresses",
|
|
|
- ""
|
|
|
-);
|
|
|
-
|
|
|
-#endif /* CONFIG_I2C_BUS1 */
|