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@@ -114,12 +114,13 @@ static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
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static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
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static int e1000_phy_reset(struct e1000_hw *hw);
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static int e1000_detect_gig_phy(struct e1000_hw *hw);
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-static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
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static void e1000_set_media_type(struct e1000_hw *hw);
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static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
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static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
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+#ifndef CONFIG_E1000_NO_NVM
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+static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
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static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
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uint16_t words,
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uint16_t *data);
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@@ -885,6 +886,7 @@ static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
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return -E1000_ERR_EEPROM;
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}
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+#endif /* CONFIG_E1000_NO_NVM */
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/*****************************************************************************
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* Set PHY to class A mode
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@@ -897,6 +899,7 @@ static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
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static int32_t
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e1000_set_phy_mode(struct e1000_hw *hw)
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{
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+#ifndef CONFIG_E1000_NO_NVM
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int32_t ret_val;
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uint16_t eeprom_data;
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@@ -923,10 +926,11 @@ e1000_set_phy_mode(struct e1000_hw *hw)
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hw->phy_reset_disable = false;
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}
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}
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-
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+#endif
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return E1000_SUCCESS;
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}
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+#ifndef CONFIG_E1000_NO_NVM
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/***************************************************************************
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*
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* Obtaining software semaphore bit (SMBI) before resetting PHY.
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@@ -965,6 +969,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
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return E1000_SUCCESS;
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}
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+#endif
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/***************************************************************************
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* This function clears HW semaphore bits.
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@@ -977,6 +982,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw)
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static void
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e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
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{
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+#ifndef CONFIG_E1000_NO_NVM
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uint32_t swsm;
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DEBUGFUNC();
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@@ -991,6 +997,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
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} else
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swsm &= ~(E1000_SWSM_SWESMBI);
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E1000_WRITE_REG(hw, SWSM, swsm);
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+#endif
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}
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/***************************************************************************
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@@ -1007,6 +1014,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
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static int32_t
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e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
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{
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+#ifndef CONFIG_E1000_NO_NVM
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int32_t timeout;
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uint32_t swsm;
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@@ -1043,7 +1051,7 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
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"SWESMBI bit is set.\n");
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return -E1000_ERR_EEPROM;
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}
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-
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+#endif
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return E1000_SUCCESS;
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}
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@@ -1097,6 +1105,7 @@ static bool e1000_is_second_port(struct e1000_hw *hw)
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}
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}
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+#ifndef CONFIG_E1000_NO_NVM
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/******************************************************************************
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* Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
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* second function of dual function devices
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@@ -1136,6 +1145,7 @@ e1000_read_mac_addr(struct eth_device *nic)
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#endif
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return 0;
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}
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+#endif
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/******************************************************************************
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* Initializes receive address filters.
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@@ -1764,9 +1774,11 @@ static int
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e1000_setup_link(struct eth_device *nic)
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{
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struct e1000_hw *hw = nic->priv;
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- uint32_t ctrl_ext;
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int32_t ret_val;
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+#ifndef CONFIG_E1000_NO_NVM
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+ uint32_t ctrl_ext;
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uint16_t eeprom_data;
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+#endif
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DEBUGFUNC();
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@@ -1775,6 +1787,7 @@ e1000_setup_link(struct eth_device *nic)
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if (e1000_check_phy_reset_block(hw))
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return E1000_SUCCESS;
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+#ifndef CONFIG_E1000_NO_NVM
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/* Read and store word 0x0F of the EEPROM. This word contains bits
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* that determine the hardware's default PAUSE (flow control) mode,
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* a bit that determines whether the HW defaults to enabling or
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@@ -1788,7 +1801,7 @@ e1000_setup_link(struct eth_device *nic)
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DEBUGOUT("EEPROM Read Error\n");
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return -E1000_ERR_EEPROM;
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}
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-
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+#endif
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if (hw->fc == e1000_fc_default) {
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switch (hw->mac_type) {
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case e1000_ich8lan:
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@@ -1797,6 +1810,7 @@ e1000_setup_link(struct eth_device *nic)
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hw->fc = e1000_fc_full;
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break;
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default:
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+#ifndef CONFIG_E1000_NO_NVM
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ret_val = e1000_read_eeprom(hw,
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EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
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if (ret_val) {
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@@ -1809,6 +1823,7 @@ e1000_setup_link(struct eth_device *nic)
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EEPROM_WORD0F_ASM_DIR)
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hw->fc = e1000_fc_tx_pause;
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else
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+#endif
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hw->fc = e1000_fc_full;
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break;
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}
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@@ -1828,6 +1843,7 @@ e1000_setup_link(struct eth_device *nic)
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DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
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+#ifndef CONFIG_E1000_NO_NVM
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/* Take the 4 bits from EEPROM word 0x0F that determine the initial
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* polarity value for the SW controlled pins, and setup the
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* Extended Device Control reg with that info.
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@@ -1840,6 +1856,7 @@ e1000_setup_link(struct eth_device *nic)
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SWDPIO__EXT_SHIFT);
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E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
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}
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+#endif
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/* Call the necessary subroutine to configure the link. */
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ret_val = (hw->media_type == e1000_media_type_fiber) ?
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@@ -5196,6 +5213,7 @@ e1000_initialize(bd_t * bis)
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e1000_reset_hw(hw);
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list_add_tail(&hw->list_node, &e1000_hw_list);
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+#ifndef CONFIG_E1000_NO_NVM
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/* Validate the EEPROM and get chipset information */
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#if !defined(CONFIG_MVBC_1G)
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if (e1000_init_eeprom_params(hw)) {
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@@ -5206,11 +5224,17 @@ e1000_initialize(bd_t * bis)
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continue;
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#endif
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e1000_read_mac_addr(nic);
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+#endif
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e1000_get_bus_type(hw);
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+#ifndef CONFIG_E1000_NO_NVM
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printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
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nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
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nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
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+#else
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+ memset(nic->enetaddr, 0, 6);
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+ printf("e1000: no NVM\n");
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+#endif
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/* Set up the function pointers and register the device */
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nic->init = e1000_init;
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