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@@ -9,7 +9,7 @@
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#ifndef __CONFIG_UNIPHIER_COMMON_H__
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#define __CONFIG_UNIPHIER_COMMON_H__
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-#if defined(CONFIG_MACH_PH1_SLD3)
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+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
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#define CONFIG_DDR_NUM_CH0 2
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#define CONFIG_DDR_NUM_CH1 1
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#define CONFIG_DDR_NUM_CH2 1
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@@ -23,7 +23,7 @@
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#define CONFIG_SDRAM2_SIZE 0x10000000
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#endif
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-#if defined(CONFIG_MACH_PH1_LD4)
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+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
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#define CONFIG_DDR_NUM_CH0 1
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#define CONFIG_DDR_NUM_CH1 1
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@@ -34,7 +34,7 @@
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#define CONFIG_SDRAM1_SIZE 0x10000000
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#endif
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-#if defined(CONFIG_MACH_PH1_PRO4)
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+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
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#define CONFIG_DDR_NUM_CH0 2
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#define CONFIG_DDR_NUM_CH1 2
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@@ -45,7 +45,7 @@
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#define CONFIG_SDRAM1_SIZE 0x20000000
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#endif
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-#if defined(CONFIG_MACH_PH1_SLD8)
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+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
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#define CONFIG_DDR_NUM_CH0 1
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#define CONFIG_DDR_NUM_CH1 1
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@@ -175,7 +175,7 @@
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#define CONFIG_NAND_DENALI_ECC_SIZE 1024
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-#ifdef CONFIG_MACH_PH1_SLD3
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+#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3
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#define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
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#define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
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#else
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@@ -291,11 +291,12 @@
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_NR_DRAM_BANKS 2
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-#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
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- defined(CONFIG_MACH_PH1_SLD8)
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+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) || \
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+ defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
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+ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
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#define CONFIG_SPL_TEXT_BASE 0x00040000
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#endif
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-#if defined(CONFIG_MACH_PH1_PRO4)
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+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
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#define CONFIG_SPL_TEXT_BASE 0x00100000
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#endif
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