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@@ -83,12 +83,6 @@
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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- clock-frequency = <24000000>;
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- arm,cpu-registers-not-fw-configured;
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- };
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-
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- memory {
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- reg = <0x40000000 0x80000000>;
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};
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clocks {
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@@ -131,15 +125,24 @@
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compatible = "allwinner,sun6i-a31-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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- clock-output-names = "pll6", "pll6x2", "pll6d2";
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+ clock-output-names = "pll6", "pll6x2";
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};
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- pll8: clk@01c20044 {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun6i-a31-pll6-clk";
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- reg = <0x01c20044 0x4>;
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- clocks = <&osc24M>;
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- clock-output-names = "pll8", "pll8x2";
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+ pll6d2: pll6d2_clk {
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+ #clock-cells = <0>;
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+ compatible = "fixed-factor-clock";
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+ clock-div = <2>;
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+ clock-mult = <1>;
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+ clocks = <&pll6 0>;
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+ clock-output-names = "pll6d2";
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+ };
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+
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+ /* dummy clock until pll6 can be reused */
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+ pll8: pll8_clk {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <1>;
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+ clock-output-names = "pll8";
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};
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cpu: cpu_clk@01c20050 {
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@@ -170,7 +173,7 @@
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-h3-ahb2-clk";
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reg = <0x01c2005c 0x4>;
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- clocks = <&ahb1>, <&pll6 2>;
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+ clocks = <&ahb1>, <&pll6d2>;
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clock-output-names = "ahb2";
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};
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@@ -213,34 +216,34 @@
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<76>, <77>, <78>,
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<96>, <97>, <98>,
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<112>, <113>,
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- <114>, <115>, <116>,
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- <128>, <135>;
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- clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0",
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- "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand",
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- "ahb1_sdram", "ahb2_gmac", "ahb1_ts",
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- "ahb1_hstimer", "ahb1_spi0",
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- "ahb1_spi1", "ahb1_otg",
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- "ahb1_otg_ehci0", "ahb1_ehic1",
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- "ahb1_ehic2", "ahb1_ehic3",
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- "ahb1_otg_ohci0", "ahb2_ohic1",
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- "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve",
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- "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint",
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- "ahb1_csi", "ahb1_tve", "ahb1_hdmi",
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- "ahb1_de", "ahb1_gpu", "ahb1_msgbox",
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- "ahb1_spinlock", "apb1_codec",
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- "apb1_spdif", "apb1_pio", "apb1_ths",
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- "apb1_i2s0", "apb1_i2s1", "apb1_i2s2",
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- "apb2_i2c0", "apb2_i2c1", "apb2_i2c2",
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- "apb2_uart0", "apb2_uart1",
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- "apb2_uart2", "apb2_uart3", "apb2_scr",
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- "ahb1_ephy", "ahb1_dbg";
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+ <114>, <115>,
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+ <116>, <128>, <135>;
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+ clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
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+ "bus_mmc1", "bus_mmc2", "bus_nand",
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+ "bus_sdram", "bus_gmac", "bus_ts",
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+ "bus_hstimer", "bus_spi0",
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+ "bus_spi1", "bus_otg",
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+ "bus_otg_ehci0", "bus_ehci1",
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+ "bus_ehci2", "bus_ehci3",
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+ "bus_otg_ohci0", "bus_ohci1",
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+ "bus_ohci2", "bus_ohci3", "bus_ve",
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+ "bus_lcd0", "bus_lcd1", "bus_deint",
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+ "bus_csi", "bus_tve", "bus_hdmi",
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+ "bus_de", "bus_gpu", "bus_msgbox",
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+ "bus_spinlock", "bus_codec",
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+ "bus_spdif", "bus_pio", "bus_ths",
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+ "bus_i2s0", "bus_i2s1", "bus_i2s2",
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+ "bus_i2c0", "bus_i2c1", "bus_i2c2",
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+ "bus_uart0", "bus_uart1",
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+ "bus_uart2", "bus_uart3",
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+ "bus_scr", "bus_ephy", "bus_dbg";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20088 0x4>;
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- clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
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+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
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clock-output-names = "mmc0",
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"mmc0_output",
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"mmc0_sample";
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@@ -250,7 +253,7 @@
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c2008c 0x4>;
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- clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
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+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
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clock-output-names = "mmc1",
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"mmc1_output",
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"mmc1_sample";
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@@ -260,7 +263,7 @@
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20090 0x4>;
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- clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
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+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
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clock-output-names = "mmc2",
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"mmc2_output",
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"mmc2_sample";
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@@ -285,6 +288,33 @@
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clocks = <&osc24M>, <&pll6 1>, <&pll5>;
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clock-output-names = "mbus";
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};
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+
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+ apb0: apb0_clk {
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+ compatible = "fixed-factor-clock";
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+ #clock-cells = <0>;
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+ clock-div = <1>;
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+ clock-mult = <1>;
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+ clocks = <&osc24M>;
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+ clock-output-names = "apb0";
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+ };
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+
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+ apb0_gates: clk@01f01428 {
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+ compatible = "allwinner,sun8i-h3-apb0-gates-clk",
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+ "allwinner,sun4i-a10-gates-clk";
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+ reg = <0x01f01428 0x4>;
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+ #clock-cells = <1>;
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+ clocks = <&apb0>;
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+ clock-indices = <0>, <1>;
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+ clock-output-names = "apb0_pio", "apb0_ir";
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+ };
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+
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+ ir_clk: ir_clk@01f01454 {
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+ compatible = "allwinner,sun4i-a10-mod0-clk";
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+ reg = <0x01f01454 0x4>;
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+ #clock-cells = <0>;
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+ clocks = <&osc32k>, <&osc24M>;
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+ clock-output-names = "ir";
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+ };
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};
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soc {
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@@ -298,7 +328,7 @@
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reg = <0x01c02000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 6>;
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- resets = <&bus_rst 6>;
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+ resets = <&ahb_rst 6>;
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#dma-cells = <1>;
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};
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@@ -313,7 +343,7 @@
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"mmc",
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"output",
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"sample";
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- resets = <&bus_rst 8>;
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+ resets = <&ahb_rst 8>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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@@ -332,7 +362,7 @@
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"mmc",
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"output",
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"sample";
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- resets = <&bus_rst 9>;
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+ resets = <&ahb_rst 9>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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@@ -351,7 +381,7 @@
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"mmc",
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"output",
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"sample";
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- resets = <&bus_rst 10>;
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+ resets = <&ahb_rst 10>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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@@ -396,7 +426,7 @@
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reg = <0x01c1b000 0x100>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 25>, <&bus_gates 29>;
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- resets = <&bus_rst 25>, <&bus_rst 29>;
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+ resets = <&ahb_rst 25>, <&ahb_rst 29>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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@@ -408,7 +438,7 @@
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 29>, <&bus_gates 25>,
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<&usb_clk 17>;
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- resets = <&bus_rst 29>, <&bus_rst 25>;
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+ resets = <&ahb_rst 29>, <&ahb_rst 25>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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@@ -419,7 +449,7 @@
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reg = <0x01c1c000 0x100>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 26>, <&bus_gates 30>;
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- resets = <&bus_rst 26>, <&bus_rst 30>;
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+ resets = <&ahb_rst 26>, <&ahb_rst 30>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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status = "disabled";
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@@ -431,7 +461,7 @@
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 30>, <&bus_gates 26>,
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<&usb_clk 18>;
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- resets = <&bus_rst 30>, <&bus_rst 26>;
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+ resets = <&ahb_rst 30>, <&ahb_rst 26>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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status = "disabled";
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@@ -442,7 +472,7 @@
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reg = <0x01c1d000 0x100>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 27>, <&bus_gates 31>;
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- resets = <&bus_rst 27>, <&bus_rst 31>;
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+ resets = <&ahb_rst 27>, <&ahb_rst 31>;
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phys = <&usbphy 3>;
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phy-names = "usb";
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status = "disabled";
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@@ -454,7 +484,7 @@
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 31>, <&bus_gates 27>,
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<&usb_clk 19>;
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- resets = <&bus_rst 31>, <&bus_rst 27>;
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+ resets = <&ahb_rst 31>, <&ahb_rst 27>;
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phys = <&usbphy 3>;
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phy-names = "usb";
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status = "disabled";
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@@ -469,7 +499,7 @@
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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- #interrupt-cells = <2>;
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+ #interrupt-cells = <3>;
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uart0_pins_a: uart0@0 {
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allwinner,pins = "PA4", "PA5";
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@@ -502,10 +532,22 @@
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};
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};
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- bus_rst: reset@01c202c0 {
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+ ahb_rst: reset@01c202c0 {
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#reset-cells = <1>;
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- compatible = "allwinner,sun8i-h3-bus-reset";
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- reg = <0x01c202c0 0x1c>;
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+ compatible = "allwinner,sun6i-a31-ahb1-reset";
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+ reg = <0x01c202c0 0xc>;
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+ };
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+
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+ apb1_rst: reset@01c202d0 {
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+ #reset-cells = <1>;
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+ compatible = "allwinner,sun6i-a31-clock-reset";
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+ reg = <0x01c202d0 0x4>;
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+ };
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+
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+ apb2_rst: reset@01c202d8 {
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+ #reset-cells = <1>;
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+ compatible = "allwinner,sun6i-a31-clock-reset";
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+ reg = <0x01c202d8 0x4>;
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};
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timer@01c20c00 {
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@@ -529,7 +571,7 @@
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&bus_gates 112>;
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- resets = <&bus_rst 144>;
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+ resets = <&apb2_rst 16>;
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dmas = <&dma 6>, <&dma 6>;
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dma-names = "rx", "tx";
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status = "disabled";
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@@ -542,7 +584,7 @@
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&bus_gates 113>;
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- resets = <&bus_rst 145>;
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+ resets = <&apb2_rst 17>;
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dmas = <&dma 7>, <&dma 7>;
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dma-names = "rx", "tx";
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status = "disabled";
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@@ -555,7 +597,7 @@
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&bus_gates 114>;
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- resets = <&bus_rst 146>;
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+ resets = <&apb2_rst 18>;
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dmas = <&dma 8>, <&dma 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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@@ -568,7 +610,7 @@
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&bus_gates 115>;
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- resets = <&bus_rst 147>;
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+ resets = <&apb2_rst 19>;
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dmas = <&dma 9>, <&dma 9>;
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dma-names = "rx", "tx";
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status = "disabled";
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@@ -591,5 +633,40 @@
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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};
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+
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+ apb0_reset: reset@01f014b0 {
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+ reg = <0x01f014b0 0x4>;
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+ compatible = "allwinner,sun6i-a31-clock-reset";
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+ #reset-cells = <1>;
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+ };
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+
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+ ir: ir@01f02000 {
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+ compatible = "allwinner,sun5i-a13-ir";
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+ clocks = <&apb0_gates 1>, <&ir_clk>;
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+ clock-names = "apb", "ir";
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+ resets = <&apb0_reset 1>;
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+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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+ reg = <0x01f02000 0x40>;
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+ status = "disabled";
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+ };
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+
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+ r_pio: pinctrl@01f02c00 {
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+ compatible = "allwinner,sun8i-h3-r-pinctrl";
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+ reg = <0x01f02c00 0x400>;
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+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&apb0_gates 0>;
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+ resets = <&apb0_reset 0>;
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+ gpio-controller;
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+ #gpio-cells = <3>;
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+
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+ ir_pins_a: ir@0 {
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+ allwinner,pins = "PL11";
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+ allwinner,function = "s_cir_rx";
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+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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+ };
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+ };
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};
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};
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