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@@ -23,6 +23,14 @@
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#include <common.h>
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#include <asm/io.h>
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+#include <asm/system.h>
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+
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+enum l2_cache_params {
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+ CACHE_TAG_RAM_SETUP = (1 << 9),
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+ CACHE_DATA_RAM_SETUP = (1 << 5),
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+ CACHE_TAG_RAM_LATENCY = (2 << 6),
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+ CACHE_DATA_RAM_LATENCY = (2 << 0)
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+};
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void reset_cpu(ulong addr)
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{
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@@ -36,3 +44,31 @@ void enable_caches(void)
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dcache_enable();
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}
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#endif
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+
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+#ifndef CONFIG_SYS_L2CACHE_OFF
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+/*
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+ * Set L2 cache parameters
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+ */
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+static void exynos5_set_l2cache_params(void)
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+{
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+ unsigned int val = 0;
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+
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+ asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
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+
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+ val |= CACHE_TAG_RAM_SETUP |
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+ CACHE_DATA_RAM_SETUP |
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+ CACHE_TAG_RAM_LATENCY |
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+ CACHE_DATA_RAM_LATENCY;
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+
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+ asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
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+}
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+
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+/*
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+ * Sets L2 cache related parameters before enabling data cache
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+ */
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+void v7_outer_cache_enable(void)
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+{
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+ if (cpu_is_exynos5())
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+ exynos5_set_l2cache_params();
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+}
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+#endif
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