Merge branch 'master' of git://git.denx.de/u-boot-rockchip

drivers/clk/rockchip/clk_rk3036.c

@@ -40,7 +40,7 @@ enum {
 			 #hz "Hz cannot be hit with PLL "\
 			 "divisors on line " __stringify(__LINE__));
 
-/* use interge mode*/
+/* use integer mode*/
 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
 
@@ -61,8 +61,8 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
 	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
 	       output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
 
-	/* use interger mode */
-	rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
+	/* use integer mode */
+	rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
 
 	rk_clrsetreg(&pll->con0,
 		     PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,

include/configs/rk3399_common.h

@@ -31,7 +31,7 @@
 #define CONFIG_SYS_LOAD_ADDR		0x00800800
 #define CONFIG_SPL_STACK		0xff8effff
 #define CONFIG_SPL_TEXT_BASE		0xff8c2000
-#define CONFIG_SPL_MAX_SIZE		0x30000
+#define CONFIG_SPL_MAX_SIZE		0x30000 - 0x2000
 /*  BSS setup */
 #define CONFIG_SPL_BSS_START_ADDR       0xff8e0000
 #define CONFIG_SPL_BSS_MAX_SIZE         0x10000

tools/rkcommon.c

@@ -76,7 +76,7 @@ static struct spl_info spl_infos[] = {
 	{ "rk3188", "RK31", 0x8000 - 0x800, true, false },
 	{ "rk3288", "RK32", 0x8000, false, false },
 	{ "rk3328", "RK32", 0x8000 - 0x1000, false, false },
-	{ "rk3399", "RK33", 0x20000, false, true },
+	{ "rk3399", "RK33", 0x30000 - 0x2000, false, true },
 	{ "rv1108", "RK11", 0x1800, false, false},
 };
 
@@ -226,11 +226,6 @@ static inline unsigned rkcommon_offset_to_spi(unsigned offset)
 	return ((offset & ~0x7ff) << 1) + (offset & 0x7ff);
 }
 
-static inline unsigned rkcommon_spi_to_offset(unsigned offset)
-{
-	return ((offset & ~0x7ff) >> 1) + (offset & 0x7ff);
-}
-
 static int rkcommon_parse_header(const void *buf, struct header0_info *header0,
 				 struct spl_info **spl_info)
 {