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@@ -87,8 +87,8 @@ static u32 polling_with_timeout(void __iomem *addr, u32 val,
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return 0;
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}
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-static int comphy_pcie_power_up(u32 lane, u32 pcie_width,
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- bool clk_src, void __iomem *hpipe_base,
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+static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
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+ bool is_end_point, void __iomem *hpipe_base,
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void __iomem *comphy_base)
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{
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u32 mask, data, ret = 1;
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@@ -109,6 +109,7 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width,
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* and SerDes Lane 0 got PCIe ref-clock #0
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*/
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debug("PCIe clock = %x\n", pcie_clk);
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+ debug("PCIe RC = %d\n", !is_end_point);
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debug("PCIe width = %d\n", pcie_width);
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/* enable PCIe by4 and by2 */
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@@ -384,10 +385,12 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width,
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data |= 0x1 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
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reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
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- /* Set phy in root complex mode */
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- mask = HPIPE_CFG_PHY_RC_EP_MASK;
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- data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET;
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- reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask);
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+ if (!is_end_point) {
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+ /* Set phy in root complex mode */
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+ mask = HPIPE_CFG_PHY_RC_EP_MASK;
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+ data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET;
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+ reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask);
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+ }
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debug("stage: Comphy power up\n");
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@@ -1667,6 +1670,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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case PHY_TYPE_PEX3:
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ret = comphy_pcie_power_up(
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lane, pcie_width, ptr_comphy_map->clk_src,
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+ serdes_map->end_point,
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hpipe_base_addr, comphy_base_addr);
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break;
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case PHY_TYPE_SATA0:
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