imx: mx6q DDR3 init: Benefit from available CL = 7

All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK
hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron
MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to
DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it.

In these conditions:
  tRCD(min) = 13.125 ns
  tRP(min) = 13.125 ns
  tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min)
  tRAS(min, DDR3-1333H) = 36 ns
  tRAS(min, DDR3-1600K) = 35 ns

MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field
MMDC1_MDCFG0[3:0].

MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded
as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18].

MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field
MMDC1_MDCFG1[2:0].

MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded
as 0x6 in the bit-field MMDC1_MDCFG1[31:29].

MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded
as 0x6 in the bit-field MMDC1_MDCFG1[28:26].

MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded
as 0x1A in the bit-field MMDC1_MDCFG1[25:21].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg

@@ -109,8 +109,8 @@ DATA 4 0x021b4828 0x33333333
 DATA 4 0x021b0018 0x00081740
 
 DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b000c 0x555A7975
-DATA 4 0x021b0010 0xFF538F64
+DATA 4 0x021b000c 0x555A7974
+DATA 4 0x021b0010 0xDB538F64
 DATA 4 0x021b0014 0x01FF00DB
 DATA 4 0x021b002c 0x000026D2
 
@@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x00008033
 DATA 4 0x021b001c 0x0000803B
 DATA 4 0x021b001c 0x00428031
 DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x19408030
-DATA 4 0x021b001c 0x19408038
+DATA 4 0x021b001c 0x19308030
+DATA 4 0x021b001c 0x19308038
 
 DATA 4 0x021b001c 0x04008040
 DATA 4 0x021b001c 0x04008048