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@@ -342,6 +342,9 @@ do { \
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#define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
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MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
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+#define MVPP22_SMI_MISC_CFG_REG 0x1204
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+#define MVPP22_SMI_POLLING_EN BIT(10)
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+
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#define MVPP22_PORT_BASE 0x30e00
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#define MVPP22_PORT_OFFSET 0x1000
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@@ -3639,9 +3642,12 @@ static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
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static void mvpp2_port_power_up(struct mvpp2_port *port)
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{
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+ struct mvpp2 *priv = port->priv;
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+
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mvpp2_port_mii_set(port);
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mvpp2_port_periodic_xon_disable(port);
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- mvpp2_port_fc_adv_enable(port);
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+ if (priv->hw_version == MVPP21)
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+ mvpp2_port_fc_adv_enable(port);
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mvpp2_port_reset(port);
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}
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@@ -3892,9 +3898,15 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
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mvpp2_conf_mbus_windows(dram_target_info, priv);
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/* Disable HW PHY polling */
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- val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
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- val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
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- writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
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+ if (priv->hw_version == MVPP21) {
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+ val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
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+ val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
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+ writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
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+ } else {
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+ val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
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+ val &= ~MVPP22_SMI_POLLING_EN;
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+ writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
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+ }
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/* Allocate and initialize aggregated TXQs */
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priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
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@@ -3920,8 +3932,9 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
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mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i),
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CONFIG_MV_ETH_RXQ);
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- writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
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- priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
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+ if (priv->hw_version == MVPP21)
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+ writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
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+ priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
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/* Allow cache snoop when transmiting packets */
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mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
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