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@@ -49,6 +49,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
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return &dpll_ddr;
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}
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+#ifdef CONFIG_REV1
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static const struct ddr_data ddr3_data = {
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.datardsratio0 = MT41J256M8HX15E_RD_DQS,
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.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
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@@ -82,6 +83,52 @@ static struct emif_regs ddr3_emif_reg_data = {
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PHY_EN_DYN_PWRDN,
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};
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+void sdram_init(void)
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+{
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+ config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
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+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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+}
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+#else
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+static const struct ddr_data ddr3_data = {
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+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
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+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
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+};
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+
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+static const struct cmd_control ddr3_cmd_ctrl_data = {
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+ .cmd0csratio = MT41K256M16HA125E_RATIO,
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+ .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
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+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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+
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+ .cmd1csratio = MT41K256M16HA125E_RATIO,
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+ .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
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+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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+
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+ .cmd2csratio = MT41K256M16HA125E_RATIO,
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+ .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
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+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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+};
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+
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+static struct emif_regs ddr3_emif_reg_data = {
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+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
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+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
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+ PHY_EN_DYN_PWRDN,
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+};
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+
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+void sdram_init(void)
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+{
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+ config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data,
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+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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+}
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+#endif
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+
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void set_uart_mux_conf(void)
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{
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enable_uart0_pin_mux();
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@@ -95,12 +142,6 @@ void set_mux_conf_regs(void)
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enable_board_pin_mux();
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}
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-
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-void sdram_init(void)
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-{
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- config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
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- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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-}
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#endif
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/*
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