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@@ -50,15 +50,13 @@
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#define CONFIG_SYS_MCKR1_VAL \
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(AT91_PMC_MCKR_CSS_SLOW | \
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AT91_PMC_MCKR_PRES_1 | \
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- AT91_PMC_MCKR_MDIV_2 | \
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- AT91_PMC_MCKR_PLLADIV_1)
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+ AT91_PMC_MCKR_MDIV_2)
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR2_VAL \
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(AT91_PMC_MCKR_CSS_PLLA | \
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AT91_PMC_MCKR_PRES_1 | \
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- AT91_PMC_MCKR_MDIV_2 | \
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- AT91_PMC_MCKR_PLLADIV_1)
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+ AT91_PMC_MCKR_MDIV_2)
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/* define PDC[31:16] as DATA[31:16] */
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#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
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