ARM: Tegra210: Add support to common Tegra source/config files

Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

arch/arm/dts/tegra210.dtsi

@@ -0,0 +1,283 @@
+#include <dt-bindings/clock/tegra210-car.h>
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "nvidia,tegra210";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	gic: interrupt-controller@0,50041000 {
+		compatible = "arm,gic-400";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x0 0x50041000 0x0 0x1000>,
+		      <0x0 0x50042000 0x0 0x2000>,
+		      <0x0 0x50044000 0x0 0x2000>,
+		      <0x0 0x50046000 0x0 0x2000>;
+		interrupts = <GIC_PPI 9
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupt-parent = <&gic>;
+	};
+
+	tegra_car: clock@0,60006000 {
+		compatible = "nvidia,tegra210-car";
+		reg = <0x0 0x60006000 0x0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	gpio: gpio@0,6000d000 {
+		compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
+		reg = <0x0 0x6000d000 0x0 0x1000>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+	};
+
+	i2c@0,7000c000 {
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+		reg = <0x0 0x7000c000 0x0 0x100>;
+		interrupts = <0 38 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 12>;
+		status = "disabled";
+	};
+
+	i2c@0,7000c400 {
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+		reg = <0x0 0x7000c400 0x0 0x100>;
+		interrupts = <0 84 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 54>;
+		status = "disabled";
+	};
+
+	i2c@0,7000c500 {
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+		reg = <0x0 0x7000c500 0x0 0x100>;
+		interrupts = <0 92 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 67>;
+		status = "disabled";
+	};
+
+	i2c@0,7000c700 {
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+		reg = <0x0 0x7000c700 0x0 0x100>;
+		interrupts = <0 120 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 103>;
+		status = "disabled";
+	};
+
+	i2c@0,7000d000 {
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+		reg = <0x0 0x7000d000 0x0 0x100>;
+		interrupts = <0 53 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 47>;
+		status = "disabled";
+	};
+
+	i2c@0,7000d100 {
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+		reg = <0x0 0x7000d100 0x0 0x100>;
+		interrupts = <0 53 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 47>;
+		status = "disabled";
+	};
+
+	uarta: serial@0,70006000 {
+		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
+		reg = <0x0 0x70006000 0x0 0x40>;
+		reg-shift = <2>;
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_UARTA>;
+		resets = <&tegra_car 6>;
+		reset-names = "serial";
+		status = "disabled";
+	};
+
+	uartb: serial@0,70006040 {
+		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
+		reg = <0x0 0x70006040 0x0 0x40>;
+		reg-shift = <2>;
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_UARTB>;
+		resets = <&tegra_car 7>;
+		reset-names = "serial";
+		status = "disabled";
+	};
+
+	uartc: serial@0,70006200 {
+		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
+		reg = <0x0 0x70006200 0x0 0x40>;
+		reg-shift = <2>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_UARTC>;
+		resets = <&tegra_car 55>;
+		reset-names = "serial";
+		status = "disabled";
+	};
+
+	uartd: serial@0,70006300 {
+		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
+		reg = <0x0 0x70006300 0x0 0x40>;
+		reg-shift = <2>;
+		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_UARTD>;
+		resets = <&tegra_car 65>;
+		reset-names = "serial";
+		status = "disabled";
+	};
+
+	spi@0,7000d400 {
+		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
+		reg = <0x0 0x7000d400 0x0 0x200>;
+		interrupts = <0 59 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car TEGRA210_CLK_SBC1>;
+		resets = <&tegra_car 41>;
+		reset-names = "spi";
+		status = "disabled";
+	};
+
+	spi@0,7000d600 {
+		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
+		reg = <0x0 0x7000d600 0x0 0x200>;
+		interrupts = <0 82 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car TEGRA210_CLK_SBC2>;
+		resets = <&tegra_car 44>;
+		reset-names = "spi";
+		status = "disabled";
+	};
+
+	spi@0,7000d800 {
+		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
+		reg = <0x0 0x7000d800 0x0 0x200>;
+		interrupts = <0 83 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car TEGRA210_CLK_SBC3>;
+		resets = <&tegra_car 46>;
+		reset-names = "spi";
+		status = "disabled";
+	};
+
+	spi@0,7000da00 {
+		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
+		reg = <0x0 0x7000da00 0x0 0x200>;
+		interrupts = <0 93 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car TEGRA210_CLK_SBC4>;
+		resets = <&tegra_car 68>;
+		reset-names = "spi";
+		status = "disabled";
+	};
+
+	spi@0,70410000 {
+		compatible = "nvidia,tegra210-qspi";
+		reg = <0x0 0x70410000 0x0 0x1000>;
+		interrupts = <0 10 0x04>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car 211>;
+		status = "disabled";
+	};
+
+	padctl: padctl@0,7009f000 {
+		compatible = "nvidia,tegra210-xusb-padctl";
+		reg = <0x0 0x7009f000 0x0 0x1000>;
+		resets = <&tegra_car 142>;
+		reset-names = "padctl";
+		#phy-cells = <1>;
+	};
+
+	sdhci@0,700b0000 {
+		compatible = "nvidia,tegra210-sdhci";
+		reg = <0x0 0x700b0000 0x0 0x200>;
+		interrupts = <0 14 0x04>;
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
+		resets = <&tegra_car 14>;
+		reset-names = "sdhci";
+		status = "disabled";
+	};
+
+	sdhci@0,700b0200 {
+		compatible = "nvidia,tegra210-sdhci";
+		reg = <0x0 0x700b0200 0x0 0x200>;
+		interrupts = <0 15 0x04>;
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
+		resets = <&tegra_car 9>;
+		reset-names = "sdhci";
+		status = "disabled";
+	};
+
+	sdhci@0,700b0400 {
+		compatible = "nvidia,tegra210-sdhci";
+		reg = <0x0 0x700b0400 0x0 0x200>;
+		interrupts = <0 19 0x04>;
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
+		resets = <&tegra_car 69>;
+		reset-names = "sdhci";
+		status = "disabled";
+	};
+
+	sdhci@0,700b0600 {
+		compatible = "nvidia,tegra210-sdhci";
+		reg = <0x0 0x700b0600 0x0 0x200>;
+		interrupts = <0 31 0x04>;
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
+		resets = <&tegra_car 15>;
+		reset-names = "sdhci";
+		status = "disabled";
+	};
+
+	usb@0,7d000000 {
+		compatible = "nvidia,tegra210-ehci";
+		reg = <0x0 0x7d000000 0x0 0x4000>;
+		interrupts = <0 20 0x04>;
+		phy_type = "utmi";
+		clocks = <&tegra_car TEGRA210_CLK_USBD>;
+		resets = <&tegra_car 22>;
+		reset-names = "usb";
+		status = "disabled";
+	};
+
+	usb@0,7d004000 {
+		compatible = "nvidia,tegra210-ehci";
+		reg = <0x0 0x7d004000 0x0 0x4000>;
+		interrupts = < 53 >;
+		phy_type = "utmi";
+		clocks = <&tegra_car TEGRA210_CLK_USB2>;
+		resets = <&tegra_car 58>;
+		reset-names = "usb";
+		status = "disabled";
+	};
+};

arch/arm/include/asm/arch-tegra/ap.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2011
+ * (C) Copyright 2010-2015
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -24,8 +24,6 @@
 #define PG_UP_TAG_0_PID_CPU	0x55555555	/* CPU aka "a9" aka "mpcore" */
 #define PG_UP_TAG_0		0x0
 
-#define CORESIGHT_UNLOCK	0xC5ACCE55;
-
 /* AP base physical address of internal SRAM */
 #define NV_PA_BASE_SRAM		0x40000000
 
@@ -66,7 +64,7 @@ int tegra_get_sku_info(void);
 /* Do any chip-specific cache config */
 void config_cache(void);
 
-#if defined(CONFIG_TEGRA124)
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
 /* Do chip-specific vpr config */
 void config_vpr(void);
 #else

arch/arm/include/asm/arch-tegra/clk_rst.h

@@ -48,6 +48,7 @@ enum {
 	TEGRA_CLK_REGS_VW	= 2,	/* Number of clock enable regs V/W */
 	TEGRA_CLK_SOURCES_VW	= 32,	/* Number of ppl clock sources V/W */
 	TEGRA_CLK_SOURCES_X	= 32,	/* Number of ppl clock sources X */
+	TEGRA_CLK_SOURCES_Y	= 18,	/* Number of ppl clock sources Y */
 };
 
 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -94,7 +95,15 @@ struct clk_rst_ctlr {
 	uint crc_rst_dev_x_set;		/* _RST_DEV_X_SET_0,	0x290 */
 	uint crc_rst_dev_x_clr;		/* _RST_DEV_X_CLR_0,	0x294 */
 
-	uint crc_reserved21[23];	/* _reserved_21,	0x298-2f0 */
+	uint crc_clk_out_enb_y;		/* _CLK_OUT_ENB_Y_0,	0x298 */
+	uint crc_clk_enb_y_set;		/* _CLK_ENB_Y_SET_0,	0x29c */
+	uint crc_clk_enb_y_clr;		/* _CLK_ENB_Y_CLR_0,	0x2a0 */
+
+	uint crc_rst_devices_y;		/* _RST_DEVICES_Y_0,	0x2a4 */
+	uint crc_rst_dev_y_set;		/* _RST_DEV_Y_SET_0,	0x2a8 */
+	uint crc_rst_dev_y_clr;		/* _RST_DEV_Y_CLR_0,	0x2ac */
+
+	uint crc_reserved21[17];	/* _reserved_21,	0x2b0-2f0 */
 
 	uint crc_dfll_base;		/* _DFLL_BASE_0,	0x2f4 */
 
@@ -136,7 +145,7 @@ struct clk_rst_ctlr {
 	struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
 	/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
 	struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
-	/* Additional (T114) registers */
+	/* Additional (T114+) registers */
 	uint crc_rst_cpug_cmplx_set;	/* _RST_CPUG_CMPLX_SET_0,  0x450 */
 	uint crc_rst_cpug_cmplx_clr;	/* _RST_CPUG_CMPLX_CLR_0,  0x454 */
 	uint crc_rst_cpulp_cmplx_set;	/* _RST_CPULP_CMPLX_SET_0, 0x458 */
@@ -207,9 +216,18 @@ struct clk_rst_ctlr {
 	u32 _rsv32_1[7];		/*                      0x574-58c */
 	struct clk_pll_simple plldp;	/* _PLLDP_BASE, 0x590 _PLLDP_MISC */
 	u32 crc_plldp_ss_cfg;		/* _PLLDP_SS_CFG, 0x598 */
-	u32 _rsrv32_2[25];
-	/* Tegra124 */
-	uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
+
+	/* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
+	uint _rsrv32_2[25];			/* _0x59C - 0x5FC */
+	uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
+
+	/* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
+	uint crc_reserved61[5];	/* _reserved_61, 0x680 - 0x690 */
+	/*
+	 * NOTE: PLLA1 regs are in the middle of this Y region. Break this in
+	 * two later if PLLA1 is needed, but for now this is cleaner.
+	 */
+	uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
 };
 
 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
@@ -233,6 +251,8 @@ struct clk_rst_ctlr {
 
 #define PLL_DIVP_SHIFT		20
 #define PLL_DIVP_MASK		(7U << PLL_DIVP_SHIFT)
+/* Special case for T210 PLLU DIVP */
+#define PLLU_DIVP_SHIFT		16
 
 #define PLL_DIVN_SHIFT		8
 #define PLL_DIVN_MASK		(0x3ffU << PLL_DIVN_SHIFT)
@@ -261,6 +281,12 @@ struct clk_rst_ctlr {
 #define PLL_LFCON_SHIFT		4
 #define PLL_LFCON_MASK		(15U << PLL_LFCON_SHIFT)
 
+/* CPCON/LFCON replaced by KCP/KVCO in T210 PLLU */
+#define PLLU_KVCO_SHIFT		24
+#define PLLU_KVCO_MASK		(3U << PLLU_KVCO_SHIFT)
+#define PLLU_KCP_SHIFT		25
+#define PLLU_KCP_MASK		(1U << PLLU_KCP_SHIFT)
+
 #define PLLU_VCO_FREQ_SHIFT	20
 #define PLLU_VCO_FREQ_MASK	(1U << PLLU_VCO_FREQ_SHIFT)
 

arch/arm/include/asm/arch-tegra/gp_padctrl.h

@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010-2012
+ *  (C) Copyright 2010-2015
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -21,5 +21,6 @@
 #define CHIPID_TEGRA30			0x30
 #define CHIPID_TEGRA114			0x35
 #define CHIPID_TEGRA124			0x40
+#define CHIPID_TEGRA210			0x21
 
 #endif	/* _TEGRA_GP_PADCTRL_H_ */

arch/arm/include/asm/arch-tegra/pmc.h

@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010,2011,2014
+ *  (C) Copyright 2010-2015
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -294,6 +294,7 @@ struct pmc_ctlr {
 #define CRAIL		0
 #define CE0		14
 #define C0NC		15
+#define SOR		17
 
 #define PMC_XOFS_SHIFT	1
 #define PMC_XOFS_MASK	(0x3F << PMC_XOFS_SHIFT)
@@ -303,7 +304,7 @@ struct pmc_ctlr {
 #define TIMER_MULT_MASK		(3 << TIMER_MULT_SHIFT)
 #define TIMER_MULT_CPU_SHIFT	2
 #define TIMER_MULT_CPU_MASK	(3 << TIMER_MULT_CPU_SHIFT)
-#elif defined(CONFIG_TEGRA124)
+#elif defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
 #define TIMER_MULT_SHIFT	0
 #define TIMER_MULT_MASK		(7 << TIMER_MULT_SHIFT)
 #define TIMER_MULT_CPU_SHIFT	3
@@ -314,7 +315,7 @@ struct pmc_ctlr {
 #define MULT_2			1
 #define MULT_4			2
 #define MULT_8			3
-#if defined(CONFIG_TEGRA124)
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
 #define MULT_16			4
 #endif
 

arch/arm/include/asm/arch-tegra/tegra.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2015
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -74,6 +74,7 @@ enum {
 	SKU_ID_T114_ENG		= 0x00, /* Dalmore value, unfused */
 	SKU_ID_T114_1		= 0x01,
 	SKU_ID_T124_ENG		= 0x00, /* Venice2 value, unfused */
+	SKU_ID_T210_ENG		= 0x00, /* unfused value TBD */
 };
 
 /*
@@ -88,6 +89,7 @@ enum {
 	TEGRA_SOC_T30,
 	TEGRA_SOC_T114,
 	TEGRA_SOC_T124,
+	TEGRA_SOC_T210,
 
 	TEGRA_SOC_CNT,
 	TEGRA_SOC_UNKNOWN	= -1,

arch/arm/include/asm/arch-tegra/usb.h

@@ -266,6 +266,9 @@ struct usb_ctlr {
 
 /* USBx_UTMIP_BIAS_CFG1_0 */
 #define UTMIP_FORCE_PDTRK_POWERDOWN		1
+#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT	8
+#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK	\
+				(0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
 #define UTMIP_BIAS_PDTRK_COUNT_SHIFT		3
 #define UTMIP_BIAS_PDTRK_COUNT_MASK		\
 				(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)

arch/arm/mach-tegra/Kconfig

@@ -34,6 +34,17 @@ config TEGRA124
 	bool "Tegra124 family"
 	select TEGRA_ARMV7_COMMON
 
+config TEGRA210
+	bool "Tegra210 family"
+	select OF_CONTROL
+	select ARM64
+	select DM
+	select DM_SPI_FLASH
+	select DM_SERIAL
+	select DM_I2C
+	select DM_SPI
+	select DM_GPIO
+
 endchoice
 
 config SYS_MALLOC_F_LEN
@@ -43,5 +54,6 @@ source "arch/arm/mach-tegra/tegra20/Kconfig"
 source "arch/arm/mach-tegra/tegra30/Kconfig"
 source "arch/arm/mach-tegra/tegra114/Kconfig"
 source "arch/arm/mach-tegra/tegra124/Kconfig"
+source "arch/arm/mach-tegra/tegra210/Kconfig"
 
 endif

arch/arm/mach-tegra/Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2010,2011 Nvidia Corporation.
+# (C) Copyright 2010-2015 Nvidia Corporation.
 #
 # (C) Copyright 2000-2008
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -24,7 +24,9 @@ obj-y += pinmux-common.o
 obj-y += powergate.o
 obj-y += xusb-padctl.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
+#TCW Fix this to use a common config switch (CONFIG_LOCK_VPR?)
 obj-$(CONFIG_TEGRA124) += vpr.o
+obj-$(CONFIG_TEGRA210) += vpr.o
 obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 
 ifndef CONFIG_SPL_BUILD
@@ -35,3 +37,4 @@ obj-$(CONFIG_TEGRA20) += tegra20/
 obj-$(CONFIG_TEGRA30) += tegra30/
 obj-$(CONFIG_TEGRA114) += tegra114/
 obj-$(CONFIG_TEGRA124) += tegra124/
+obj-$(CONFIG_TEGRA210) += tegra210/

arch/arm/mach-tegra/ap.c

@@ -1,5 +1,5 @@
 /*
-* (C) Copyright 2010-2014
+* (C) Copyright 2010-2015
 * NVIDIA Corporation <www.nvidia.com>
 *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -92,6 +92,13 @@ int tegra_get_chip_sku(void)
 			return TEGRA_SOC_T124;
 		}
 		break;
+	case CHIPID_TEGRA210:
+		switch (sku_id) {
+		case SKU_ID_T210_ENG:
+		default:
+			return TEGRA_SOC_T210;
+		}
+		break;
 	}
 
 	/* unknown chip/sku id */
@@ -100,6 +107,7 @@ int tegra_get_chip_sku(void)
 	return TEGRA_SOC_UNKNOWN;
 }
 
+#ifndef CONFIG_ARM64
 static void enable_scu(void)
 {
 	struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
@@ -222,3 +230,4 @@ void s_init(void)
 	/* init vpr */
 	config_vpr();
 }
+#endif

arch/arm/mach-tegra/board.c

@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010-2014
+ *  (C) Copyright 2010-2015
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -143,12 +143,18 @@ static int uart_configs[] = {
 	-1,
 	FUNCMUX_UART4_GMI,	/* UARTD */
 	-1,
-#else	/* Tegra124 */
+#elif defined(CONFIG_TEGRA124)
 	FUNCMUX_UART1_KBC,	/* UARTA */
 	-1,
 	-1,
 	FUNCMUX_UART4_GPIO,	/* UARTD */
 	-1,
+#else	/* Tegra210 */
+	FUNCMUX_UART1_UART1,	/* UARTA */
+	-1,
+	-1,
+	FUNCMUX_UART4_UART4,	/* UARTD */
+	-1,
 #endif
 };
 

arch/arm/mach-tegra/cache.c

@@ -21,6 +21,7 @@
 #include <asm/arch-tegra/ap.h>
 #include <asm/arch/gp_padctrl.h>
 
+#ifndef CONFIG_ARM64
 void config_cache(void)
 {
 	u32 reg = 0;
@@ -44,3 +45,4 @@ void config_cache(void)
 	reg |= 2;
 	asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
 }
+#endif

arch/arm/mach-tegra/clock.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -113,7 +113,11 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
 	data = readl(&pll->pll_misc);
 	*cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
 	*lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
-
+#if defined(CONFIG_TEGRA210)
+	/* T210 PLLU uses KCP/KVCO instead of CPCON/LFCON */
+	*cpcon = (data & PLLU_KCP_MASK) >> PLLU_KCP_SHIFT;
+	*lfcon = (data & PLLU_KVCO_MASK) >> PLLU_KVCO_SHIFT;
+#endif
 	return 0;
 }
 
@@ -132,14 +136,28 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
 	 * - same fields are always mapped at same offsets, except DCCON
 	 * - DCCON is always 0, doesn't conflict
 	 * - M,N, P of PLLP values are ignored for PLLP
+	 * NOTE: Above is no longer true with T210 - TBD: FIX THIS
 	 */
 	misc_data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
 
+#if defined(CONFIG_TEGRA210)
+	/* T210 PLLU uses KCP/KVCO instead of cpcon/lfcon */
+	if (clkid == CLOCK_ID_USB) {
+		/* preserve EN_LOCKDET, set by default */
+		misc_data = readl(&pll->pll_misc);
+		misc_data |= (cpcon << PLLU_KCP_SHIFT) |
+			(lfcon << PLLU_KVCO_SHIFT);
+	}
+#endif
 	data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
 			(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
 
 	if (clkid == CLOCK_ID_USB)
+#if defined(CONFIG_TEGRA210)
+		data |= divp << PLLU_DIVP_SHIFT;
+#else
 		data |= divp << PLLU_VCO_FREQ_SHIFT;
+#endif
 	else
 		data |= divp << PLL_DIVP_SHIFT;
 	if (pll) {
@@ -534,8 +552,15 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
 
 	/* Set cpcon to PLL_MISC */
 	misc_reg = readl(&pll->pll_misc);
+#if !defined(CONFIG_TEGRA210)
 	misc_reg &= ~PLL_CPCON_MASK;
 	misc_reg |= cpcon << PLL_CPCON_SHIFT;
+#else
+	/* T210 uses KCP instead, use the most common bit shift (PLLA/U/D2) */
+	misc_reg &= ~PLLU_KCP_MASK;
+	misc_reg |= cpcon << PLLU_KCP_SHIFT;
+#endif
+
 	writel(misc_reg, &pll->pll_misc);
 
 	/* Enable PLL */
@@ -628,6 +653,7 @@ static void set_avp_clock_source(u32 src)
 /*
  * This function is useful on Tegra30, and any later SoCs that have compatible
  * PLLP configuration registers.
+ * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
  */
 void tegra30_set_up_pllp(void)
 {

arch/arm/mach-tegra/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -29,6 +29,7 @@ int get_num_cpus(void)
 {
 	struct apb_misc_gp_ctlr *gp;
 	uint rev;
+	debug("%s entry\n", __func__);
 
 	gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
@@ -39,6 +40,8 @@ int get_num_cpus(void)
 		break;
 	case CHIPID_TEGRA30:
 	case CHIPID_TEGRA114:
+	case CHIPID_TEGRA124:
+	case CHIPID_TEGRA210:
 	default:
 		return 4;
 		break;
@@ -128,13 +131,30 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
 		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
 		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
 	},
+
+	/*
+	 * T210: 700 MHz
+	 *
+	 * Register   Field  Bits   Width
+	 * ------------------------------
+	 * PLLX_BASE  p      24:20    5
+	 * PLLX_BASE  n      15: 8    8
+	 * PLLX_BASE  m       7: 0    8
+	 */
+	{
+		{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702   MHz*/
+		{ .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
+		{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696   MHz*/
+		{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702   MHz*/
+	},
 };
 
 static inline void pllx_set_iddq(void)
 {
-#if defined(CONFIG_TEGRA124)
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
 	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 	u32 reg;
+	debug("%s entry\n", __func__);
 
 	/* Disable IDDQ */
 	reg = readl(&clkrst->crc_pllx_misc3);
@@ -151,15 +171,14 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
 {
 	int chip = tegra_get_chip();
 	u32 reg;
+	debug("%s entry\n", __func__);
 
 	/* If PLLX is already enabled, just return */
 	if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
-		debug("pllx_set_rate: PLLX already enabled, returning\n");
+		debug("%s: PLLX already enabled, returning\n", __func__);
 		return 0;
 	}
 
-	debug(" pllx_set_rate entry\n");
-
 	pllx_set_iddq();
 
 	/* Set BYPASS, m, n and p to PLLX_BASE */
@@ -182,19 +201,19 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
 	reg = readl(&pll->pll_base);
 	reg &= ~PLL_BYPASS_MASK;
 	writel(reg, &pll->pll_base);
-	debug("pllx_set_rate: base = 0x%08X\n", reg);
+	debug("%s: base = 0x%08X\n", __func__, reg);
 
 	/* Set lock_enable to PLLX_MISC */
 	reg = readl(&pll->pll_misc);
 	reg |= PLL_LOCK_ENABLE_MASK;
 	writel(reg, &pll->pll_misc);
-	debug("pllx_set_rate: misc = 0x%08X\n", reg);
+	debug("%s: misc = 0x%08X\n", __func__, reg);
 
 	/* Enable PLLX last, once it's all configured */
 	reg = readl(&pll->pll_base);
 	reg |= PLL_ENABLE_MASK;
 	writel(reg, &pll->pll_base);
-	debug("pllx_set_rate: base final = 0x%08X\n", reg);
+	debug("%s: base final = 0x%08X\n", __func__, reg);
 
 	return 0;
 }
@@ -206,24 +225,23 @@ void init_pllx(void)
 	int soc_type, sku_info, chip_sku;
 	enum clock_osc_freq osc;
 	struct clk_pll_table *sel;
-
-	debug("init_pllx entry\n");
+	debug("%s entry\n", __func__);
 
 	/* get SOC (chip) type */
 	soc_type = tegra_get_chip();
-	debug(" init_pllx: SoC = 0x%02X\n", soc_type);
+	debug("%s: SoC = 0x%02X\n", __func__, soc_type);
 
 	/* get SKU info */
 	sku_info = tegra_get_sku_info();
-	debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
+	debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
 
 	/* get chip SKU, combo of the above info */
 	chip_sku = tegra_get_chip_sku();
-	debug(" init_pllx: Chip SKU = %d\n", chip_sku);
+	debug("%s: Chip SKU = %d\n", __func__, chip_sku);
 
 	/* get osc freq */
 	osc = clock_get_osc_freq();
-	debug(" init_pllx: osc = %d\n", osc);
+	debug("%s: osc = %d\n", __func__, osc);
 
 	/* set pllx */
 	sel = &tegra_pll_x_table[chip_sku][osc];
@@ -234,6 +252,7 @@ void enable_cpu_clock(int enable)
 {
 	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 	u32 clk;
+	debug("%s entry\n", __func__);
 
 	/*
 	 * NOTE:
@@ -282,6 +301,7 @@ static void remove_cpu_io_clamps(void)
 {
 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	u32 reg;
+	debug("%s entry\n", __func__);
 
 	/* Remove the clamps on the CPU I/O signals */
 	reg = readl(&pmc->pmc_remove_clamping);
@@ -297,6 +317,7 @@ void powerup_cpu(void)
 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 	u32 reg;
 	int timeout = IO_STABILIZATION_DELAY;
+	debug("%s entry\n", __func__);
 
 	if (!is_cpu_powered()) {
 		/* Toggle the CPU power state (OFF -> ON) */
@@ -336,7 +357,7 @@ void reset_A9_cpu(int reset)
 	int num_cpus = get_num_cpus();
 	int cpu;
 
-	debug("reset_a9_cpu entry\n");
+	debug("%s entry\n", __func__);
 	/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
 	for (cpu = 1; cpu < num_cpus; cpu++)
 		reset_cmplx_set_enable(cpu, mask, 1);
@@ -350,7 +371,7 @@ void clock_enable_coresight(int enable)
 {
 	u32 rst, src = 2;
 
-	debug("clock_enable_coresight entry\n");
+	debug("%s entry\n", __func__);
 	clock_set_enable(PERIPH_ID_CORESIGHT, enable);
 	reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
 
@@ -377,6 +398,8 @@ void clock_enable_coresight(int enable)
 
 void halt_avp(void)
 {
+	debug("%s entry\n", __func__);
+
 	for (;;) {
 		writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
 		       FLOW_CTLR_HALT_COP_EVENTS);

arch/arm/mach-tegra/cpu.h

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2014
+ * (C) Copyright 2010-2015
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -14,7 +14,7 @@
 #define NVBL_PLLP_KHZ	216000
 #define CSITE_KHZ	144000
 #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
-	defined(CONFIG_TEGRA124)
+	defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
 #define NVBL_PLLP_KHZ	408000
 #define CSITE_KHZ	204000
 #else
@@ -35,7 +35,7 @@
 #define PG_UP_TAG_0_PID_CPU	0x55555555	/* CPU aka "a9" aka "mpcore" */
 #define PG_UP_TAG_0             0x0
 
-#define CORESIGHT_UNLOCK	0xC5ACCE55;
+#define CORESIGHT_UNLOCK	0xC5ACCE55
 
 #define EXCEP_VECTOR_CPU_RESET_VECTOR	(NV_PA_EVP_BASE + 0x100)
 #define CSITE_CPU_DBG0_LAR		(NV_PA_CSITE_BASE + 0x10FB0)
@@ -53,6 +53,10 @@
 
 #define SIMPLE_PLLX     (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
 
+/* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */
+#define SB_AA64_RESET_LOW	0x6000C230
+#define SB_AA64_RESET_HIGH	0x6000C234
+
 struct clk_pll_table {
 	u16	n;
 	u16	m;

arch/arm/mach-tegra/lowlevel_init.S

@@ -10,6 +10,20 @@
 #include <config.h>
 #include <linux/linkage.h>
 
+#ifdef CONFIG_ARM64
+	.align	5
+ENTRY(reset_cpu)
+	/* get address for global reset register */
+	ldr	x1, =PRM_RSTCTRL
+	ldr	w3, [x1]
+	/* force reset */
+	orr	w3, w3, #0x10
+	str	w3, [x1]
+	mov	w0, w0
+1:
+	b	1b
+ENDPROC(reset_cpu)
+#else
 	.align	5
 ENTRY(reset_cpu)
 	ldr	r1, rstctl			@ get addr for global reset
@@ -23,3 +37,4 @@ _loop_forever:
 rstctl:
 	.word	PRM_RSTCTRL
 ENDPROC(reset_cpu)
+#endif

drivers/mmc/tegra_mmc.c

@@ -2,7 +2,7 @@
  * (C) Copyright 2009 SAMSUNG Electronics
  * Minkyu Kang <mk7.kang@samsung.com>
  * Jaehoon Chung <jh80.chung@samsung.com>
- * Portions Copyright 2011-2013 NVIDIA Corporation
+ * Portions Copyright 2011-2015 NVIDIA Corporation
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -668,6 +668,16 @@ void tegra_mmc_init(void)
 	const void *blob = gd->fdt_blob;
 	debug("%s entry\n", __func__);
 
+	/* See if any Tegra210 MMC controllers are present */
+	count = fdtdec_find_aliases_for_id(blob, "sdhci",
+		COMPAT_NVIDIA_TEGRA210_SDMMC, node_list,
+		CONFIG_SYS_MMC_MAX_DEVICE);
+	debug("%s: count of Tegra210 sdhci nodes is %d\n", __func__, count);
+	if (process_nodes(blob, node_list, count)) {
+		printf("%s: Error processing T30 mmc node(s)!\n", __func__);
+		return;
+	}
+
 	/* See if any Tegra124 MMC controllers are present */
 	count = fdtdec_find_aliases_for_id(blob, "sdhci",
 		COMPAT_NVIDIA_TEGRA124_SDMMC, node_list,

drivers/usb/host/ehci-tegra.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
- * Copyright (c) 2009-2013 NVIDIA Corporation
+ * Copyright (c) 2009-2015 NVIDIA Corporation
  * Copyright (c) 2013 Lucas Stach
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -64,6 +64,7 @@ enum usb_ctlr_type {
 	USB_CTLR_T20,
 	USB_CTLR_T30,
 	USB_CTLR_T114,
+	USB_CTLR_T210,
 
 	USB_CTRL_COUNT,
 };
@@ -149,6 +150,15 @@ static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
 	{ 0x3C0, 0x1A, 0x00, 0xC,   2,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB }
 };
 
+/* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */
+static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
+	/* DivN, DivM, DivP, KCP,   KVCO,  Delays              Debounce, Bias */
+	{ 0x028, 0x01, 0x01, 0x0,   0,  0x02, 0x2F, 0x08, 0x76,  30000,  5 },
+	{ 0x019, 0x01, 0x01, 0x0,   0,  0x03, 0x4B, 0x0C, 0xBB,  48000,  8 },
+	{ 0x028, 0x01, 0x01, 0x0,   0,  0x02, 0x2F, 0x08, 0x76,  30000,  5 },
+	{ 0x028, 0x01, 0x01, 0x0,   0,  0x02, 0x2F, 0x08, 0x76,  30000,  5 },
+};
+
 /* UTMIP Idle Wait Delay */
 static const u8 utmip_idle_wait_delay = 17;
 
@@ -177,6 +187,10 @@ static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = {
 		.has_hostpc	= 1,
 		.pll_parameter	= (const unsigned *)T114_usb_pll,
 	},
+	{
+		.has_hostpc	= 1,
+		.pll_parameter	= (const unsigned *)T210_usb_pll,
+	},
 };
 
 /*
@@ -458,6 +472,16 @@ static int init_utmi_usb_controller(struct fdt_usb *config,
 		UTMIP_DEBOUNCE_CFG0_MASK,
 		timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
 
+	if (timing[PARAM_DEBOUNCE_A_TIME] > 0xFFFF) {
+		clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
+				UTMIP_DEBOUNCE_CFG0_MASK,
+				(timing[PARAM_DEBOUNCE_A_TIME] >> 1)
+				<< UTMIP_DEBOUNCE_CFG0_SHIFT);
+		clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
+				UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK,
+				1 << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT);
+	}
+
 	setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
 
 	/* Disable battery charge enabling bit */
@@ -643,6 +667,10 @@ static int init_ulpi_usb_controller(struct fdt_usb *config,
 
 static void config_clock(const u32 timing[])
 {
+	debug("%s: DIVM = %d, DIVN = %d, DIVP = %d, cpcon/lfcon = %d/%d\n",
+	      __func__, timing[PARAM_DIVM], timing[PARAM_DIVN],
+	      timing[PARAM_DIVP], timing[PARAM_CPCON], timing[PARAM_LFCON]);
+
 	clock_start_pll(CLOCK_ID_USB,
 		timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
 		timing[PARAM_CPCON], timing[PARAM_LFCON]);
@@ -823,6 +851,7 @@ static const struct udevice_id ehci_usb_ids[] = {
 	{ .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 },
 	{ .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 },
 	{ .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 },
+	{ .compatible = "nvidia,tegra210-ehci", .data = USB_CTLR_T210 },
 	{ }
 };
 

include/configs/tegra-common-post.h

@@ -62,11 +62,19 @@
 #define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
 #endif
 
+#ifdef CONFIG_ARM64
+#define FDT_HIGH "ffffffffffffffff"
+#define INITRD_HIGH "ffffffffffffffff"
+#else
+#define FDT_HIGH "ffffffff"
+#define INITRD_HIGH "ffffffff"
+#endif
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	TEGRA_DEVICE_SETTINGS \
 	MEM_LAYOUT_ENV_SETTINGS \
-	"fdt_high=ffffffff\0" \
-	"initrd_high=ffffffff\0" \
+	"fdt_high=" FDT_HIGH "\0" \
+	"initrd_high=" INITRD_HIGH "\0" \
 	BOOTENV \
 	BOARD_EXTRA_ENV_SETTINGS \
 	CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS

include/fdtdec.h

@@ -137,6 +137,7 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA124_SOR,	/* Tegra 124 Serial Output Resource */
 	COMPAT_NVIDIA_TEGRA124_PMC,	/* Tegra 124 power mgmt controller */
 	COMPAT_NVIDIA_TEGRA20_DC,	/* Tegra 2 Display controller */
+	COMPAT_NVIDIA_TEGRA210_SDMMC,	/* Tegra210 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA124_SDMMC,	/* Tegra124 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA30_SDMMC,	/* Tegra30 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA20_SDMMC,	/* Tegra20 SDMMC controller */
@@ -145,6 +146,8 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA20_PCIE,	/* Tegra 20 PCIe controller */
 	COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
 					/* Tegra124 XUSB pad controller */
+	COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
+					/* Tegra210 XUSB pad controller */
 	COMPAT_SMSC_LAN9215,		/* SMSC 10/100 Ethernet LAN9215 */
 	COMPAT_SAMSUNG_EXYNOS5_SROMC,	/* Exynos5 SROMC */
 	COMPAT_SAMSUNG_S3C2440_I2C,	/* Exynos I2C Controller */

lib/fdtdec.c

@@ -31,6 +31,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"),
 	COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
 	COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+	COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
 	COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
 	COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
 	COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
@@ -38,6 +39,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA30_PCIE, "nvidia,tegra30-pcie"),
 	COMPAT(NVIDIA_TEGRA20_PCIE, "nvidia,tegra20-pcie"),
 	COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
+	COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
 	COMPAT(SMSC_LAN9215, "smsc,lan9215"),
 	COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
 	COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),