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@@ -251,6 +251,10 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
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u32 val, step, old, reg = readl(&anatop->reg_core);
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u8 shift;
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+ /* No LDO_SOC/PU/ARM */
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+ if (is_mx6sll())
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+ return 0;
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+
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if (mv < 725)
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val = 0x00; /* Power gated off */
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else if (mv > 1450)
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@@ -310,7 +314,7 @@ static void clear_mmdc_ch_mask(void)
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reg = readl(&mxc_ccm->ccdr);
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/* Clear MMDC channel mask */
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- if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl())
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+ if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl() || is_mx6sll())
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reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
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else
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reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
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@@ -512,6 +516,10 @@ uint mmc_get_env_part(struct mmc *mmc)
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int board_postclk_init(void)
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{
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+ /* NO LDO SOC on i.MX6SLL */
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+ if (is_mx6sll())
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+ return 0;
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+
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set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
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return 0;
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@@ -593,7 +601,7 @@ void s_init(void)
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u32 mask528;
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u32 reg, periph1, periph2;
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- if (is_mx6sx() || is_mx6ul() || is_mx6ull())
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+ if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
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return;
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/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
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