boards/c29xpcie: Update TLB and LAW size for IFC NAND, CPLD

 NAND,CPLD AMASK register is programmed for 64K size.

so Update TLB & LAW size accordingly.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>

board/freescale/c29xpcie/law.c

@@ -10,8 +10,8 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_16K, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
 	SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
 					LAW_TRGT_IF_PLATFORM_SRAM),
 };

board/freescale/c29xpcie/tlb.c

@@ -46,11 +46,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 4, BOOKE_PAGESZ_4K, 1),
+			0, 4, BOOKE_PAGESZ_64K, 1),
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 			MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 5, BOOKE_PAGESZ_16K, 1),
+			0, 5, BOOKE_PAGESZ_64K, 1),
 
 	SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
 			CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,