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+/*
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+ * Copyright (C) 2015 Udoo
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+ * Author: Tungyi Lin <tungyilin1127@gmail.com>
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+ * Richard Hu <hakahu@gmail.com>
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+ * Based on board/wandboard/spl.c
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#include <asm/arch/clock.h>
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+#include <asm/arch/imx-regs.h>
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+#include <asm/arch/iomux.h>
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+#include <asm/arch/mx6-pins.h>
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+#include <asm/errno.h>
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+#include <asm/gpio.h>
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+#include <asm/imx-common/iomux-v3.h>
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+#include <asm/imx-common/video.h>
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+#include <mmc.h>
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+#include <fsl_esdhc.h>
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+#include <asm/arch/crm_regs.h>
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+#include <asm/io.h>
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+#include <asm/arch/sys_proto.h>
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+#include <spl.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+#if defined(CONFIG_SPL_BUILD)
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+#include <asm/arch/mx6-ddr.h>
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+
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+/*
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+ * Driving strength:
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+ * 0x30 == 40 Ohm
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+ * 0x28 == 48 Ohm
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+ */
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+#define IMX6DQ_DRIVE_STRENGTH 0x30
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+#define IMX6SDL_DRIVE_STRENGTH 0x28
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+
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+/* configure MX6Q/DUAL mmdc DDR io registers */
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+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
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+ .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_cas = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_ras = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_reset = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_sdba2 = 0x00000000,
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+ .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
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+ .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
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+};
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+
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+/* configure MX6Q/DUAL mmdc GRP io registers */
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+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
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+ .grp_ddr_type = 0x000c0000,
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+ .grp_ddrmode_ctl = 0x00020000,
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+ .grp_ddrpke = 0x00000000,
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+ .grp_addds = IMX6DQ_DRIVE_STRENGTH,
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+ .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
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+ .grp_ddrmode = 0x00020000,
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+ .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
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+ .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
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+ .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
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+ .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
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+ .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
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+ .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
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+ .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
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+ .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
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+};
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+
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+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
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+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
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+ .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_cas = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_ras = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_reset = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdba2 = 0x00000000,
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+ .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
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+};
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+
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+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
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+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
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+ .grp_ddr_type = 0x000c0000,
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+ .grp_ddrmode_ctl = 0x00020000,
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+ .grp_ddrpke = 0x00000000,
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+ .grp_addds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_ddrmode = 0x00020000,
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+ .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
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+};
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+
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+/* MT41K128M16JT-125 */
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+static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
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+ /* quad = 1066, duallite = 800 */
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+ .mem_speed = 1066,
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+ .density = 2,
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+ .width = 16,
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+ .banks = 8,
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+ .rowaddr = 14,
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+ .coladdr = 10,
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+ .pagesz = 2,
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+ .trcd = 1375,
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+ .trcmin = 4875,
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+ .trasmin = 3500,
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+ .SRT = 0,
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+};
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+
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+static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
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+ .p0_mpwldectrl0 = 0x00350035,
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+ .p0_mpwldectrl1 = 0x001F001F,
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+ .p1_mpwldectrl0 = 0x00010001,
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+ .p1_mpwldectrl1 = 0x00010001,
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+ .p0_mpdgctrl0 = 0x43510360,
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+ .p0_mpdgctrl1 = 0x0342033F,
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+ .p1_mpdgctrl0 = 0x033F033F,
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+ .p1_mpdgctrl1 = 0x03290266,
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+ .p0_mprddlctl = 0x4B3E4141,
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+ .p1_mprddlctl = 0x47413B4A,
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+ .p0_mpwrdlctl = 0x42404843,
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+ .p1_mpwrdlctl = 0x4C3F4C45,
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+};
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+
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+static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
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+ .p0_mpwldectrl0 = 0x002F0038,
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+ .p0_mpwldectrl1 = 0x001F001F,
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+ .p1_mpwldectrl0 = 0x001F001F,
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+ .p1_mpwldectrl1 = 0x001F001F,
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+ .p0_mpdgctrl0 = 0x425C0251,
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+ .p0_mpdgctrl1 = 0x021B021E,
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+ .p1_mpdgctrl0 = 0x021B021E,
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+ .p1_mpdgctrl1 = 0x01730200,
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+ .p0_mprddlctl = 0x45474C45,
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+ .p1_mprddlctl = 0x44464744,
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+ .p0_mpwrdlctl = 0x3F3F3336,
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+ .p1_mpwrdlctl = 0x32383630,
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+};
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+
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+/* DDR 64bit 1GB */
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+static struct mx6_ddr_sysinfo mem_qdl = {
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+ .dsize = 2,
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+ .cs1_mirror = 0,
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+ /* config for full 4GB range so that get_mem_size() works */
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+ .cs_density = 32,
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+ .ncs = 1,
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+ .bi_on = 1,
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+ /* quad = 2, duallite = 1 */
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+ .rtt_nom = 2,
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+ /* quad = 2, duallite = 1 */
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+ .rtt_wr = 2,
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+ .ralat = 5,
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+ .walat = 0,
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+ .mif3_mode = 3,
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+ .rst_to_cke = 0x23,
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+ .sde_to_rst = 0x10,
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+};
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+
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+static void ccgr_init(void)
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+{
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+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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+
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+ /* set the default clock gate to save power */
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+ writel(0x00C03F3F, &ccm->CCGR0);
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+ writel(0x0030FC03, &ccm->CCGR1);
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+ writel(0x0FFFC000, &ccm->CCGR2);
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+ writel(0x3FF00000, &ccm->CCGR3);
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+ writel(0x00FFF300, &ccm->CCGR4);
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+ writel(0x0F0000C3, &ccm->CCGR5);
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+ writel(0x000003FF, &ccm->CCGR6);
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+}
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+
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+static void gpr_init(void)
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+{
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+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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+
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+ /* enable AXI cache for VDOA/VPU/IPU */
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+ writel(0xF00000FF, &iomux->gpr[4]);
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+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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+ writel(0x007F007F, &iomux->gpr[6]);
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+ writel(0x007F007F, &iomux->gpr[7]);
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+}
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+
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+static void spl_dram_init(void)
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+{
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+ if (is_cpu_type(MXC_CPU_MX6DL)) {
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+ mt41k128m16jt_125.mem_speed = 800;
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+ mem_qdl.rtt_nom = 1;
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+ mem_qdl.rtt_wr = 1;
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+
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+ mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
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+ mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
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+ } else if (is_cpu_type(MXC_CPU_MX6Q)) {
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+ mt41k128m16jt_125.mem_speed = 1066;
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+ mem_qdl.rtt_nom = 2;
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+ mem_qdl.rtt_wr = 2;
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+
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+ mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
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+ mx6_dram_cfg(&mem_qdl, &mx6q_1g_mmdc_calib, &mt41k128m16jt_125);
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+ }
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+
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+ udelay(100);
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+}
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+
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+void board_init_f(ulong dummy)
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+{
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+ ccgr_init();
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+
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+ /* setup AIPS and disable watchdog */
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+ arch_cpu_init();
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+
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+ gpr_init();
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+
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+ /* iomux */
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+ board_early_init_f();
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+
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+ /* setup GP timer */
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+ timer_init();
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+
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+ /* UART clocks enabled and gd valid - init serial console */
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+ preloader_console_init();
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+
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+ /* DDR initialization */
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+ spl_dram_init();
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+
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+ /* Clear the BSS. */
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+ memset(__bss_start, 0, __bss_end - __bss_start);
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+
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+ /* load/boot image from boot device */
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+ board_init_r(NULL, 0);
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+}
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+#endif
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vpeter4