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@@ -551,43 +551,6 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
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eeprom->use_eerd = true;
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eeprom->use_eewr = false;
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break;
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-
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- /* ich8lan does not support currently. if needed, please
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- * add corresponding code and functions.
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- */
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-#if 0
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- case e1000_ich8lan:
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- {
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- int32_t i = 0;
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-
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- eeprom->type = e1000_eeprom_ich8;
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- eeprom->use_eerd = false;
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- eeprom->use_eewr = false;
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- eeprom->word_size = E1000_SHADOW_RAM_WORDS;
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- uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
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- ICH_FLASH_GFPREG);
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- /* Zero the shadow RAM structure. But don't load it from NVM
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- * so as to save time for driver init */
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- if (hw->eeprom_shadow_ram != NULL) {
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- for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
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- hw->eeprom_shadow_ram[i].modified = false;
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- hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
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- }
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- }
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-
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- hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
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- ICH_FLASH_SECTOR_SIZE;
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-
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- hw->flash_bank_size = ((flash_size >> 16)
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- & ICH_GFPREG_BASE_MASK) + 1;
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- hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
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-
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- hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
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-
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- hw->flash_bank_size /= 2 * sizeof(uint16_t);
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- break;
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- }
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-#endif
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default:
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break;
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}
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@@ -838,14 +801,6 @@ e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
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if (eeprom->use_eerd == true)
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return e1000_read_eeprom_eerd(hw, offset, words, data);
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- /* ich8lan does not support currently. if needed, please
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- * add corresponding code and functions.
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- */
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-#if 0
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- /* ICH EEPROM access is done via the ICH flash controller */
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- if (eeprom->type == e1000_eeprom_ich8)
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- return e1000_read_eeprom_ich8(hw, offset, words, data);
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-#endif
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/* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
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* acquired the EEPROM at this point, so any returns should relase it */
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if (eeprom->type == e1000_eeprom_spi) {
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@@ -1732,17 +1687,7 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
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* occuring when accessing our register space */
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E1000_WRITE_FLUSH(hw);
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}
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-#if 0
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- /* Set the PCI priority bit correctly in the CTRL register. This
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- * determines if the adapter gives priority to receives, or if it
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- * gives equal priority to transmits and receives. Valid only on
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- * 82542 and 82543 silicon.
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- */
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- if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
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- ctrl = E1000_READ_REG(hw, CTRL);
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- E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
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- }
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-#endif
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+
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switch (hw->mac_type) {
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case e1000_82545_rev_3:
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case e1000_82546_rev_3:
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@@ -1842,20 +1787,6 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
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break;
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}
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-#if 0
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- /* Clear all of the statistics registers (clear on read). It is
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- * important that we do this after we have tried to establish link
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- * because the symbol error count will increment wildly if there
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- * is no link.
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- */
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- e1000_clear_hw_cntrs(hw);
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-
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- /* ICH8 No-snoop bits are opposite polarity.
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- * Set to snoop by default after reset. */
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- if (hw->mac_type == e1000_ich8lan)
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- e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
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-#endif
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-
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if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
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hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
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ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
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@@ -5230,10 +5161,6 @@ _e1000_disable(struct e1000_hw *hw)
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E1000_WRITE_REG(hw, RDH, 0);
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E1000_WRITE_REG(hw, RDT, 0);
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- /* put the card in its initial state */
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-#if 0
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- E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
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-#endif
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mdelay(10);
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}
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@@ -5359,7 +5286,6 @@ static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
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#ifndef CONFIG_E1000_NO_NVM
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/* Validate the EEPROM and get chipset information */
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-#if !defined(CONFIG_MVBC_1G)
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if (e1000_init_eeprom_params(hw)) {
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E1000_ERR(hw, "EEPROM is invalid!\n");
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return -EINVAL;
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@@ -5367,7 +5293,6 @@ static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
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if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
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e1000_validate_eeprom_checksum(hw))
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return -ENXIO;
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-#endif
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e1000_read_mac_addr(hw, enetaddr);
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#endif
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e1000_get_bus_type(hw);
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