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@@ -174,9 +174,9 @@
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#endif
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/* controller 2, Slot 2, tgtid 2, Base address 9000 */
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-#if defined(CONFIG_P1010RDB_PA)
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+#if defined(CONFIG_TARGET_P1010RDB_PA)
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#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
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-#elif defined(CONFIG_P1010RDB_PB)
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+#elif defined(CONFIG_TARGET_P1010RDB_PB)
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#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
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#endif
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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@@ -378,7 +378,7 @@ extern unsigned long get_sdram_size(void);
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| CSPR_V)
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#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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-#if defined(CONFIG_P1010RDB_PA)
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+#if defined(CONFIG_TARGET_P1010RDB_PA)
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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@@ -388,7 +388,7 @@ extern unsigned long get_sdram_size(void);
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| CSOR_NAND_PB(32)) /* 32 Pages Per Block */
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#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
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-#elif defined(CONFIG_P1010RDB_PB)
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+#elif defined(CONFIG_TARGET_P1010RDB_PB)
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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@@ -404,7 +404,7 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_CMD_NAND
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-#if defined(CONFIG_P1010RDB_PA)
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+#if defined(CONFIG_TARGET_P1010RDB_PA)
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/* NAND Flash Timing Params */
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#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
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FTIM0_NAND_TWP(0x0C) | \
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@@ -419,7 +419,7 @@ extern unsigned long get_sdram_size(void);
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FTIM2_NAND_TWHRE(0x0f)
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#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
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-#elif defined(CONFIG_P1010RDB_PB)
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+#elif defined(CONFIG_TARGET_P1010RDB_PB)
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/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
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/* ONFI NAND Flash mode0 Timing Params */
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#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
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@@ -592,7 +592,7 @@ extern unsigned long get_sdram_size(void);
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#define I2C_PCA9557_BUS_NUM 0
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/* I2C EEPROM */
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-#if defined(CONFIG_P1010RDB_PB)
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+#if defined(CONFIG_TARGET_P1010RDB_PB)
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#define CONFIG_ID_EEPROM
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#ifdef CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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@@ -718,10 +718,10 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
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#else
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-#if defined(CONFIG_P1010RDB_PA)
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+#if defined(CONFIG_TARGET_P1010RDB_PA)
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
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-#elif defined(CONFIG_P1010RDB_PB)
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+#elif defined(CONFIG_TARGET_P1010RDB_PB)
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#define CONFIG_ENV_SIZE (16 * 1024)
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#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
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#endif
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@@ -842,7 +842,7 @@ extern unsigned long get_sdram_size(void);
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"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
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CONFIG_BOOTMODE
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-#if defined(CONFIG_P1010RDB_PA)
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+#if defined(CONFIG_TARGET_P1010RDB_PA)
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#define CONFIG_BOOTMODE \
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"boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
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"mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
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@@ -851,7 +851,7 @@ extern unsigned long get_sdram_size(void);
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"boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
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"mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
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-#elif defined(CONFIG_P1010RDB_PB)
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+#elif defined(CONFIG_TARGET_P1010RDB_PB)
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#define CONFIG_BOOTMODE \
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"boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
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"i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
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