ARM: keystone2: Remove unsed external clocks

Remove unused external clocks and make a common definition
for all keystone platforms.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

arch/arm/mach-keystone/clock-k2e.c

@@ -43,7 +43,7 @@ static unsigned long pll_freq_get(int pll)
 			reg = KS2_PASSPLLCTL0;
 			break;
 		case DDR3_PLL:
-			ret = external_clk[ddr3_clk];
+			ret = external_clk[ddr3a_clk];
 			reg = KS2_DDR3APLLCTL0;
 			break;
 		default:

arch/arm/mach-keystone/clock-k2l.c

@@ -47,7 +47,7 @@ static unsigned long pll_freq_get(int pll)
 			reg = KS2_ARMPLLCTL0;
 			break;
 		case DDR3_PLL:
-			ret = external_clk[ddr3_clk];
+			ret = external_clk[ddr3a_clk];
 			reg = KS2_DDR3APLLCTL0;
 			break;
 		default:

arch/arm/mach-keystone/include/mach/clock-k2e.h

@@ -10,21 +10,6 @@
 #ifndef __ASM_ARCH_CLOCK_K2E_H
 #define __ASM_ARCH_CLOCK_K2E_H
 
-enum ext_clk_e {
-	sys_clk,
-	alt_core_clk,
-	pa_clk,
-	ddr3_clk,
-	mcm_clk,
-	pcie_clk,
-	sgmii_clk,
-	xgmii_clk,
-	usb_clk,
-	ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
 #define CLK_LIST(CLK)\
 	CLK(0, core_pll_clk)\
 	CLK(1, pass_pll_clk)\

arch/arm/mach-keystone/include/mach/clock-k2hk.h

@@ -10,24 +10,6 @@
 #ifndef __ASM_ARCH_CLOCK_K2HK_H
 #define __ASM_ARCH_CLOCK_K2HK_H
 
-enum ext_clk_e {
-	sys_clk,
-	alt_core_clk,
-	pa_clk,
-	tetris_clk,
-	ddr3a_clk,
-	ddr3b_clk,
-	mcm_clk,
-	pcie_clk,
-	sgmii_srio_clk,
-	xgmii_clk,
-	usb_clk,
-	rp1_clk,
-	ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
 #define CLK_LIST(CLK)\
 	CLK(0, core_pll_clk)\
 	CLK(1, pass_pll_clk)\

arch/arm/mach-keystone/include/mach/clock-k2l.h

@@ -10,21 +10,6 @@
 #ifndef __ASM_ARCH_CLOCK_K2L_H
 #define __ASM_ARCH_CLOCK_K2L_H
 
-enum ext_clk_e {
-	sys_clk,
-	alt_core_clk,
-	pa_clk,
-	tetris_clk,
-	ddr3_clk,
-	pcie_clk,
-	sgmii_clk,
-	usb_clk,
-	rp1_clk,
-	ext_clk_count /* number of external clocks */
-};
-
-extern unsigned int external_clk[ext_clk_count];
-
 #define CLK_LIST(CLK)\
 	CLK(0, core_pll_clk)\
 	CLK(1, pass_pll_clk)\

arch/arm/mach-keystone/include/mach/clock.h

@@ -55,6 +55,16 @@ enum {
 	MAX_PLL_COUNT,
 };
 
+enum ext_clk_e {
+	sys_clk,
+	alt_core_clk,
+	pa_clk,
+	tetris_clk,
+	ddr3a_clk,
+	ddr3b_clk,
+	ext_clk_count /* number of external clocks */
+};
+
 enum clk_e {
 	CLK_LIST(GENERATE_ENUM)
 };
@@ -72,6 +82,7 @@ struct pll_init_data {
 	int pll_od;		/* PLL output divider */
 };
 
+extern unsigned int external_clk[ext_clk_count];
 extern const struct keystone_pll_regs keystone_pll_regs[];
 extern s16 divn_val[];
 extern int speeds[];

board/ti/ks2_evm/board_k2e.c

@@ -18,12 +18,7 @@ unsigned int external_clk[ext_clk_count] = {
 	[sys_clk]	= 100000000,
 	[alt_core_clk]	= 100000000,
 	[pa_clk]	= 100000000,
-	[ddr3_clk]	= 100000000,
-	[mcm_clk]	= 312500000,
-	[pcie_clk]	= 100000000,
-	[sgmii_clk]	= 156250000,
-	[xgmii_clk]	= 156250000,
-	[usb_clk]	= 100000000,
+	[ddr3a_clk]	= 100000000,
 };
 
 static struct pll_init_data core_pll_config[NUM_SPDS] = {

board/ti/ks2_evm/board_k2hk.c

@@ -21,12 +21,6 @@ unsigned int external_clk[ext_clk_count] = {
 	[tetris_clk]	=	125000000,
 	[ddr3a_clk]	=	100000000,
 	[ddr3b_clk]	=	100000000,
-	[mcm_clk]	=	312500000,
-	[pcie_clk]	=	100000000,
-	[sgmii_srio_clk] =	156250000,
-	[xgmii_clk]	=	156250000,
-	[usb_clk]	=	100000000,
-	[rp1_clk]	=	123456789
 };
 
 static struct pll_init_data core_pll_config[NUM_SPDS] = {

board/ti/ks2_evm/board_k2l.c

@@ -19,10 +19,7 @@ unsigned int external_clk[ext_clk_count] = {
 	[alt_core_clk]	= 100000000,
 	[pa_clk]	= 122880000,
 	[tetris_clk]	= 122880000,
-	[ddr3_clk]	= 100000000,
-	[pcie_clk]	= 100000000,
-	[sgmii_clk]	= 156250000,
-	[usb_clk]	= 100000000,
+	[ddr3a_clk]	= 100000000,
 };
 
 static struct pll_init_data core_pll_config[NUM_SPDS] = {