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powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P5020 and P5040

Secure Boot Target is added for NAND for P5020 and P5040.
The Secure boot target has already been added for P3041 by
enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM.

The targets for P5020 and P5040 are added in the same manner.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Aneesh Bansal 10 년 전
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3개의 변경된 파일12개의 추가작업 그리고 0개의 파일을 삭제
  1. 2 0
      board/freescale/corenet_ds/MAINTAINERS
  2. 5 0
      configs/P5020DS_NAND_SECURE_BOOT_defconfig
  3. 5 0
      configs/P5040DS_NAND_SECURE_BOOT_defconfig

+ 2 - 0
board/freescale/corenet_ds/MAINTAINERS

@@ -33,3 +33,5 @@ CORENET_DS_SECURE_BOOT BOARD
 M:	Aneesh Bansal <aneesh.bansal@freescale.com>
 S:	Maintained
 F:	configs/P3041DS_NAND_SECURE_BOOT_defconfig
+F:	configs/P5020DS_NAND_SECURE_BOOT_defconfig
+F:	configs/P5040DS_NAND_SECURE_BOOT_defconfig

+ 5 - 0
configs/P5020DS_NAND_SECURE_BOOT_defconfig

@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P5020DS=y
+CONFIG_SPI_FLASH=y

+ 5 - 0
configs/P5040DS_NAND_SECURE_BOOT_defconfig

@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P5040DS=y
+CONFIG_SPI_FLASH=y