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powerpc: mpc85xx: Move CONFIG_SYS_FSL_QORIQ_CHASSIS* to Kconfig

Use Kconfig option to select chassis version.

Signed-off-by: York Sun <york.sun@nxp.com>
York Sun 8 years ago
parent
9ec10107e1
commit
7371774ab9
3 changed files with 21 additions and 12 deletions
Unified View Show Diff Stats
  1. 21 0
      arch/powerpc/cpu/mpc85xx/Kconfig
  2. 0 10
      arch/powerpc/include/asm/config_mpc85xx.h
  3. 0 2
      scripts/config_whitelist.txt

+ 21 - 0
arch/powerpc/cpu/mpc85xx/Kconfig
View File 

@@ -345,6 +345,7 @@ config ARCH_B4420
 
 	select SYS_FSL_ERRATUM_A009942
 
 	select SYS_FSL_ERRATUM_A009942
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS2
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_4
 
 	select SYS_FSL_SEC_COMPAT_4
 
 
 
@@ -366,6 +367,7 @@ config ARCH_B4860
 
 	select SYS_FSL_ERRATUM_A009942
 
 	select SYS_FSL_ERRATUM_A009942
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS2
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_4
 
 	select SYS_FSL_SEC_COMPAT_4
 
 
 
@@ -646,6 +648,7 @@ config ARCH_P2041
 
 	select SYS_FSL_ERRATUM_USB14
 
 	select SYS_FSL_ERRATUM_USB14
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS1
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_4
 
 	select SYS_FSL_SEC_COMPAT_4
 
 
 
@@ -668,6 +671,7 @@ config ARCH_P3041
 
 	select SYS_FSL_ERRATUM_USB14
 
 	select SYS_FSL_ERRATUM_USB14
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS1
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_4
 
 	select SYS_FSL_SEC_COMPAT_4
 
 
 
@@ -701,6 +705,7 @@ config ARCH_P4080
 
 	select SYS_P4080_ERRATUM_SERDES_A005
 
 	select SYS_P4080_ERRATUM_SERDES_A005
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS1
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_4
 
 	select SYS_FSL_SEC_COMPAT_4
 
 
 
@@ -719,6 +724,7 @@ config ARCH_P5020
 
 	select SYS_FSL_ERRATUM_USB14
 
 	select SYS_FSL_ERRATUM_USB14
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS1
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_4
 
 	select SYS_FSL_SEC_COMPAT_4
 
 
 
@@ -737,6 +743,7 @@ config ARCH_P5040
 
 	select SYS_FSL_ERRATUM_USB14
 
 	select SYS_FSL_ERRATUM_USB14
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS1
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_4
 
 	select SYS_FSL_SEC_COMPAT_4
 
 
 
@@ -755,6 +762,7 @@ config ARCH_T1023
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR4
 
 	select SYS_FSL_HAS_DDR4
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS2
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_5
 
 	select SYS_FSL_SEC_COMPAT_5
 
 
 
@@ -770,6 +778,7 @@ config ARCH_T1024
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR4
 
 	select SYS_FSL_HAS_DDR4
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS2
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_5
 
 	select SYS_FSL_SEC_COMPAT_5
 
 
 
@@ -786,6 +795,7 @@ config ARCH_T1040
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR4
 
 	select SYS_FSL_HAS_DDR4
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS2
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_5
 
 	select SYS_FSL_SEC_COMPAT_5
 
 
 
@@ -802,6 +812,7 @@ config ARCH_T1042
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR4
 
 	select SYS_FSL_HAS_DDR4
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS2
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_5
 
 	select SYS_FSL_SEC_COMPAT_5
 
 
 
@@ -819,6 +830,7 @@ config ARCH_T2080
 
 	select SYS_FSL_ERRATUM_ESDHC111
 
 	select SYS_FSL_ERRATUM_ESDHC111
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS2
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_4
 
 	select SYS_FSL_SEC_COMPAT_4
 
 
 
@@ -836,6 +848,7 @@ config ARCH_T2081
 
 	select SYS_FSL_ERRATUM_ESDHC111
 
 	select SYS_FSL_ERRATUM_ESDHC111
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS2
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_4
 
 	select SYS_FSL_SEC_COMPAT_4
 
 
 
@@ -854,6 +867,7 @@ config ARCH_T4160
 
 	select SYS_FSL_ERRATUM_A009942
 
 	select SYS_FSL_ERRATUM_A009942
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS2
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_4
 
 	select SYS_FSL_SEC_COMPAT_4
 
 
 
@@ -873,6 +887,7 @@ config ARCH_T4240
 
 	select SYS_FSL_ERRATUM_A009942
 
 	select SYS_FSL_ERRATUM_A009942
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_DDR3
 
 	select SYS_FSL_HAS_SEC
 
 	select SYS_FSL_HAS_SEC
 
+	select SYS_FSL_QORIQ_CHASSIS2
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_BE
 
 	select SYS_FSL_SEC_COMPAT_4
 
 	select SYS_FSL_SEC_COMPAT_4
 
 
 
@@ -1132,6 +1147,12 @@ config SYS_P4080_ERRATUM_SERDES_A001
 
 config SYS_P4080_ERRATUM_SERDES_A005
 
 config SYS_P4080_ERRATUM_SERDES_A005
 
 	bool
 
 	bool
 
 
 
+config SYS_FSL_QORIQ_CHASSIS1
 
+	bool
 
+
 
+config SYS_FSL_QORIQ_CHASSIS2
 
+	bool
 
+
 
 config SYS_FSL_NUM_LAWS
 
 config SYS_FSL_NUM_LAWS
 
 	int "Number of local access windows"
 
 	int "Number of local access windows"
 
 	depends on FSL_LAW
 
 	depends on FSL_LAW

+ 0 - 10
arch/powerpc/include/asm/config_mpc85xx.h
View File 

@@ -117,7 +117,6 @@
 
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
 
 
 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
 
 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
 
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
 #define CONFIG_SYS_NUM_FMAN		1
 
 #define CONFIG_SYS_NUM_FMAN		1
 
@@ -136,7 +135,6 @@
 
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 
 
 #elif defined(CONFIG_ARCH_P3041)
 
 #elif defined(CONFIG_ARCH_P3041)
 
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
 #define CONFIG_SYS_NUM_FMAN		1
 
 #define CONFIG_SYS_NUM_FMAN		1
 
@@ -155,7 +153,6 @@
 
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 
 
 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
 
 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
 
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
 
 #define CONFIG_SYS_NUM_FMAN		2
 
 #define CONFIG_SYS_NUM_FMAN		2
 
@@ -176,7 +173,6 @@
 
 
 
 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
 
 #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
 
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
 #define CONFIG_SYS_NUM_FMAN		1
 
 #define CONFIG_SYS_NUM_FMAN		1
 
@@ -196,7 +192,6 @@
 
 
 
 #elif defined(CONFIG_ARCH_P5040)
 
 #elif defined(CONFIG_ARCH_P5040)
 
 #define CONFIG_SYS_PPC64
 
 #define CONFIG_SYS_PPC64
 
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	3
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	3
 
 #define CONFIG_SYS_NUM_FMAN		2
 
 #define CONFIG_SYS_NUM_FMAN		2
 
@@ -240,7 +235,6 @@
 
 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
 
 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
 
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
 
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
 
 #ifdef CONFIG_ARCH_T4240
 
 #ifdef CONFIG_ARCH_T4240
 
@@ -285,7 +279,6 @@
 
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
 
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
 
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
 
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
 
 #define CONFIG_HETROGENOUS_CLUSTERS     /* DSP/SC3900 core clusters */
 
 #define CONFIG_HETROGENOUS_CLUSTERS     /* DSP/SC3900 core clusters */
 
 #define CONFIG_PPC_CLUSTER_START	0 /*Start index of ppc clusters*/
 
 #define CONFIG_PPC_CLUSTER_START	0 /*Start index of ppc clusters*/
 
@@ -334,7 +327,6 @@
 
 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
 
 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
 
 #define CONFIG_E5500
 
 #define CONFIG_E5500
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
 
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
@@ -367,7 +359,6 @@
 
 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
 
 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
 
 #define CONFIG_E5500
 
 #define CONFIG_E5500
 
 #define CONFIG_FSL_CORENET	     /* Freescale CoreNet platform */
 
 #define CONFIG_FSL_CORENET	     /* Freescale CoreNet platform */
 
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
 
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 
 #define CONFIG_SYS_FSL_QMAN_V3	 /* QMAN version 3 */
 
 #define CONFIG_SYS_FSL_QMAN_V3	 /* QMAN version 3 */
 
 #define CONFIG_SYS_FMAN_V3
 
 #define CONFIG_SYS_FMAN_V3
 
@@ -399,7 +390,6 @@
 
 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
 
 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
 
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 
-#define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 
 #define CONFIG_SYS_FSL_QMAN_V3
 
 #define CONFIG_SYS_FSL_QMAN_V3

+ 0 - 2
scripts/config_whitelist.txt
View File 

@@ -5459,8 +5459,6 @@ CONFIG_SYS_FSL_QBMAN_SIZE_1
 
 CONFIG_SYS_FSL_QMAN_ADDR
 
 CONFIG_SYS_FSL_QMAN_ADDR
 
 CONFIG_SYS_FSL_QMAN_OFFSET
 
 CONFIG_SYS_FSL_QMAN_OFFSET
 
 CONFIG_SYS_FSL_QMAN_V3
 
 CONFIG_SYS_FSL_QMAN_V3
 
-CONFIG_SYS_FSL_QORIQ_CHASSIS1
 
-CONFIG_SYS_FSL_QORIQ_CHASSIS2
 
 CONFIG_SYS_FSL_QSPI_AHB
 
 CONFIG_SYS_FSL_QSPI_AHB
 
 CONFIG_SYS_FSL_QSPI_BASE
 
 CONFIG_SYS_FSL_QSPI_BASE
 
 CONFIG_SYS_FSL_QSPI_BASE1
 
 CONFIG_SYS_FSL_QSPI_BASE1