Merge git://git.denx.de/u-boot-uniphier

arch/arm/dts/uniphier-ld11.dtsi

@@ -352,6 +352,7 @@
 				 <&mio_clk 12>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 				 <&mio_rst 12>;
+			has-transaction-translator;
 		};
 
 		usb1: usb@5a810100 {
@@ -365,6 +366,7 @@
 				 <&mio_clk 13>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 				 <&mio_rst 13>;
+			has-transaction-translator;
 		};
 
 		usb2: usb@5a820100 {
@@ -378,6 +380,7 @@
 				 <&mio_clk 14>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 				 <&mio_rst 14>;
+			has-transaction-translator;
 		};
 
 		mioctrl@5b3e0000 {

arch/arm/dts/uniphier-ld4.dtsi

@@ -276,6 +276,7 @@
 				 <&mio_clk 12>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 				 <&mio_rst 12>;
+			has-transaction-translator;
 		};
 
 		usb1: usb@5a810100 {
@@ -289,6 +290,7 @@
 				 <&mio_clk 13>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 				 <&mio_rst 13>;
+			has-transaction-translator;
 		};
 
 		usb2: usb@5a820100 {
@@ -302,6 +304,7 @@
 				 <&mio_clk 14>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 				 <&mio_rst 14>;
+			has-transaction-translator;
 		};
 
 		soc-glue@5f800000 {
@@ -314,6 +317,24 @@
 			};
 		};
 
+		soc-glue@5f900000 {
+			compatible = "socionext,uniphier-ld4-soc-glue-debug",
+				     "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x5f900000 0x2000>;
+
+			efuse@100 {
+				compatible = "socionext,uniphier-efuse";
+				reg = <0x100 0x28>;
+			};
+
+			efuse@130 {
+				compatible = "socionext,uniphier-efuse";
+				reg = <0x130 0x8>;
+			};
+		};
+
 		timer@60000200 {
 			compatible = "arm,cortex-a9-global-timer";
 			reg = <0x60000200 0x20>;

arch/arm/dts/uniphier-pro4-ref.dts

@@ -91,3 +91,7 @@
 &usb1 {
 	status = "okay";
 };
+
+&nand {
+	status = "okay";
+};

arch/arm/dts/uniphier-pro4.dtsi

@@ -327,6 +327,7 @@
 				 <&mio_clk 12>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 				 <&mio_rst 12>;
+			has-transaction-translator;
 		};
 
 		usb3: usb@5a810100 {
@@ -340,6 +341,7 @@
 				 <&mio_clk 13>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 				 <&mio_rst 13>;
+			has-transaction-translator;
 		};
 
 		soc-glue@5f800000 {
@@ -352,6 +354,29 @@
 			};
 		};
 
+		soc-glue@5f900000 {
+			compatible = "socionext,uniphier-pro4-soc-glue-debug",
+				     "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x5f900000 0x2000>;
+
+			efuse@100 {
+				compatible = "socionext,uniphier-efuse";
+				reg = <0x100 0x28>;
+			};
+
+			efuse@130 {
+				compatible = "socionext,uniphier-efuse";
+				reg = <0x130 0x8>;
+			};
+
+			efuse@200 {
+				compatible = "socionext,uniphier-efuse";
+				reg = <0x200 0x14>;
+			};
+		};
+
 		aidet: aidet@5fc20000 {
 			compatible = "socionext,uniphier-pro4-aidet";
 			reg = <0x5fc20000 0x200>;

arch/arm/dts/uniphier-pro5.dtsi

@@ -359,6 +359,39 @@
 			};
 		};
 
+		soc-glue@5f900000 {
+			compatible = "socionext,uniphier-pro5-soc-glue-debug",
+				     "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x5f900000 0x2000>;
+
+			efuse@100 {
+				compatible = "socionext,uniphier-efuse";
+				reg = <0x100 0x28>;
+			};
+
+			efuse@130 {
+				compatible = "socionext,uniphier-efuse";
+				reg = <0x130 0x8>;
+			};
+
+			efuse@200 {
+				compatible = "socionext,uniphier-efuse";
+				reg = <0x200 0x28>;
+			};
+
+			efuse@300 {
+				compatible = "socionext,uniphier-efuse";
+				reg = <0x300 0x14>;
+			};
+
+			efuse@400 {
+				compatible = "socionext,uniphier-efuse";
+				reg = <0x400 0x8>;
+			};
+		};
+
 		aidet: aidet@5fc20000 {
 			compatible = "socionext,uniphier-pro5-aidet";
 			reg = <0x5fc20000 0x200>;

arch/arm/dts/uniphier-pxs2.dtsi

@@ -415,6 +415,24 @@
 			};
 		};
 
+		soc-glue@5f900000 {
+			compatible = "socionext,uniphier-pxs2-soc-glue-debug",
+				     "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x5f900000 0x2000>;
+
+			efuse@100 {
+				compatible = "socionext,uniphier-efuse";
+				reg = <0x100 0x28>;
+			};
+
+			efuse@200 {
+				compatible = "socionext,uniphier-efuse";
+				reg = <0x200 0x58>;
+			};
+		};
+
 		aidet: aidet@5fc20000 {
 			compatible = "socionext,uniphier-pxs2-aidet";
 			reg = <0x5fc20000 0x200>;

arch/arm/dts/uniphier-pxs3-ref.dts

@@ -45,6 +45,14 @@
 	status = "okay";
 };
 
+&serial2 {
+	status = "okay";
+};
+
+&serial3 {
+	status = "okay";
+};
+
 &gpio {
 	xirq4 {
 		gpio-hog;

arch/arm/dts/uniphier-pxs3.dtsi

@@ -203,8 +203,8 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 			gpio-ranges = <&pinctrl 0 0 0>,
-				      <&pinctrl 96 0 0>,
-				      <&pinctrl 160 0 0>;
+				      <&pinctrl 104 0 0>,
+				      <&pinctrl 168 0 0>;
 			gpio-ranges-group-names = "gpio_range0",
 						  "gpio_range1",
 						  "gpio_range2";

arch/arm/dts/uniphier-sld8.dtsi

@@ -280,6 +280,7 @@
 				 <&mio_clk 12>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 				 <&mio_rst 12>;
+			has-transaction-translator;
 		};
 
 		usb1: usb@5a810100 {
@@ -293,6 +294,7 @@
 				 <&mio_clk 13>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 				 <&mio_rst 13>;
+			has-transaction-translator;
 		};
 
 		usb2: usb@5a820100 {
@@ -306,6 +308,7 @@
 				 <&mio_clk 14>;
 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 				 <&mio_rst 14>;
+			has-transaction-translator;
 		};
 
 		soc-glue@5f800000 {
@@ -318,6 +321,24 @@
 			};
 		};
 
+		soc-glue@5f900000 {
+			compatible = "socionext,uniphier-sld8-soc-glue-debug",
+				     "simple-mfd";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0x5f900000 0x2000>;
+
+			efuse@100 {
+				compatible = "socionext,uniphier-efuse";
+				reg = <0x100 0x28>;
+			};
+
+			efuse@200 {
+				compatible = "socionext,uniphier-efuse";
+				reg = <0x200 0x14>;
+			};
+		};
+
 		timer@60000200 {
 			compatible = "arm,cortex-a9-global-timer";
 			reg = <0x60000200 0x20>;

include/configs/uniphier.h

@@ -87,7 +87,7 @@
 #define CONFIG_GATEWAYIP		192.168.11.1
 #define CONFIG_NETMASK			255.255.255.0
 
-#define CONFIG_LOADADDR			0x84000000
+#define CONFIG_LOADADDR			0x85000000
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
 #define CONFIG_SYS_BOOTM_LEN		(32 << 20)
 
@@ -115,7 +115,7 @@
 #define CONFIG_BOOTFILE			"fitImage"
 #define LINUXBOOT_ENV_SETTINGS \
 	"fit_addr=0x00100000\0" \
-	"fit_addr_r=0x84100000\0" \
+	"fit_addr_r=0x85100000\0" \
 	"fit_size=0x00f00000\0" \
 	"norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
 		"bootm $fit_addr\0" \
@@ -128,7 +128,7 @@
 #ifdef CONFIG_ARM64
 #define CONFIG_BOOTFILE			"Image.gz"
 #define LINUXBOOT_CMD			"booti"
-#define KERNEL_ADDR_LOAD		"kernel_addr_load=0x84200000\0"
+#define KERNEL_ADDR_LOAD		"kernel_addr_load=0x85200000\0"
 #define KERNEL_ADDR_R			"kernel_addr_r=0x82080000\0"
 #else
 #define CONFIG_BOOTFILE			"zImage"
@@ -138,15 +138,15 @@
 #endif
 #define LINUXBOOT_ENV_SETTINGS \
 	"fdt_addr=0x00100000\0" \
-	"fdt_addr_r=0x84100000\0" \
+	"fdt_addr_r=0x85100000\0" \
 	"fdt_size=0x00008000\0" \
 	"kernel_addr=0x00200000\0" \
 	KERNEL_ADDR_LOAD \
 	KERNEL_ADDR_R \
-	"kernel_size=0x00800000\0" \
-	"ramdisk_addr=0x00a00000\0" \
-	"ramdisk_addr_r=0x84a00000\0" \
-	"ramdisk_size=0x00600000\0" \
+	"kernel_size=0x00e00000\0" \
+	"ramdisk_addr=0x01000000\0" \
+	"ramdisk_addr_r=0x86000000\0" \
+	"ramdisk_size=0x00800000\0" \
 	"ramdisk_file=rootfs.cpio.uboot\0" \
 	"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \
 		"if test $kernel_addr_load = $kernel_addr_r; then " \
@@ -192,17 +192,17 @@
 		"tftpboot $second_image && " \
 		"mmc write $loadaddr 0 100 && " \
 		"tftpboot $third_image && " \
-		"mmc write $loadaddr 100 700\0" \
+		"mmc write $loadaddr 100 f00\0" \
 	"nandupdate=nand erase 0 0x00100000 &&"			\
 		"tftpboot $second_image && " \
 		"nand write $loadaddr 0 0x00020000 && " \
 		"tftpboot $third_image && " \
-		"nand write $loadaddr 0x00020000 0x000e0000\0" \
+		"nand write $loadaddr 0x00020000 0x001e0000\0" \
 	"usbupdate=usb start &&" \
 		"tftpboot $second_image && " \
 		"usb write $loadaddr 0 100 && " \
 		"tftpboot $third_image && " \
-		"usb write $loadaddr 100 700\0" \
+		"usb write $loadaddr 100 f00\0" \
 	BOOT_IMAGES \
 	LINUXBOOT_ENV_SETTINGS