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@@ -157,9 +157,11 @@ static const struct sys_mmu_table early_mmu_table[] = {
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{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
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CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
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{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
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- CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
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+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
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+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
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- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
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+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
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+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
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#endif
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};
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@@ -245,7 +247,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
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CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
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{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
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- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
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+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
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+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
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{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
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CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
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@@ -256,7 +259,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
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CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
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{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
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- CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
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+ CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
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+ PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
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#endif
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};
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#endif
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