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@@ -771,6 +771,16 @@ int enable_lcdif_clock(u32 base_addr)
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return 0;
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}
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+ /* Gate LCDIF clock first */
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+ reg = readl(&imx_ccm->CCGR3);
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+ reg &= ~lcdif_ccgr3_mask;
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+ writel(reg, &imx_ccm->CCGR3);
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+
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+ reg = readl(&imx_ccm->CCGR2);
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+ reg &= ~MXC_CCM_CCGR2_LCD_MASK;
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+ writel(reg, &imx_ccm->CCGR2);
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+
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+ /* Select pre-mux */
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reg = readl(&imx_ccm->cscdr2);
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reg &= ~lcdif_clk_sel_mask;
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writel(reg, &imx_ccm->cscdr2);
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