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@@ -43,9 +43,12 @@
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*/
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#include <dt-bindings/clock/sun50i-a64-ccu.h>
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+#include <dt-bindings/clock/sun8i-de2.h>
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#include <dt-bindings/clock/sun8i-r-ccu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/sun50i-a64-ccu.h>
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+#include <dt-bindings/reset/sun8i-de2.h>
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+#include <dt-bindings/reset/sun8i-r-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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@@ -57,17 +60,21 @@
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#size-cells = <1>;
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ranges;
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-/*
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- * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU.
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- * However there is no support for this clock on A64 yet, so we depend
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- * on the upstream clocks here to keep them (and thus CLK_MIXER0) up.
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- */
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simplefb_lcd: framebuffer-lcd {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "mixer0-lcd0";
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clocks = <&ccu CLK_TCON0>,
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- <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
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+ <&display_clocks CLK_MIXER0>;
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+ status = "disabled";
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+ };
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+
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+ simplefb_hdmi: framebuffer-hdmi {
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+ compatible = "allwinner,simple-framebuffer",
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+ "simple-framebuffer";
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+ allwinner,pipeline = "mixer1-lcd1-hdmi";
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+ clocks = <&display_clocks CLK_MIXER1>,
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+ <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
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status = "disabled";
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};
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};
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@@ -81,6 +88,7 @@
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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+ next-level-cache = <&L2>;
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};
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cpu1: cpu@1 {
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@@ -88,6 +96,7 @@
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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+ next-level-cache = <&L2>;
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};
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cpu2: cpu@2 {
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@@ -95,6 +104,7 @@
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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+ next-level-cache = <&L2>;
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};
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cpu3: cpu@3 {
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@@ -102,7 +112,20 @@
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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+ next-level-cache = <&L2>;
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};
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+
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+ L2: l2-cache {
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+ compatible = "cache";
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+ cache-level = <2>;
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+ };
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+ };
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+
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+ de: display-engine {
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+ compatible = "allwinner,sun50i-a64-display-engine";
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+ allwinner,pipelines = <&mixer0>,
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+ <&mixer1>;
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+ status = "disabled";
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};
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osc24M: osc24M_clk {
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@@ -168,10 +191,93 @@
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#size-cells = <1>;
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ranges;
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+ de2@1000000 {
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+ compatible = "allwinner,sun50i-a64-de2";
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+ reg = <0x1000000 0x400000>;
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+ allwinner,sram = <&de2_sram 1>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0x1000000 0x400000>;
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+
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+ display_clocks: clock@0 {
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+ compatible = "allwinner,sun50i-a64-de2-clk";
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+ reg = <0x0 0x100000>;
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+ clocks = <&ccu CLK_DE>,
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+ <&ccu CLK_BUS_DE>;
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+ clock-names = "mod",
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+ "bus";
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+ resets = <&ccu RST_BUS_DE>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ mixer0: mixer@100000 {
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+ compatible = "allwinner,sun50i-a64-de2-mixer-0";
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+ reg = <0x100000 0x100000>;
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+ clocks = <&display_clocks CLK_BUS_MIXER0>,
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+ <&display_clocks CLK_MIXER0>;
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+ clock-names = "bus",
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+ "mod";
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+ resets = <&display_clocks RST_MIXER0>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ mixer0_out: port@1 {
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+ reg = <1>;
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+
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+ mixer0_out_tcon0: endpoint {
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+ remote-endpoint = <&tcon0_in_mixer0>;
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+ };
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+ };
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+ };
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+ };
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+
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+ mixer1: mixer@200000 {
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+ compatible = "allwinner,sun50i-a64-de2-mixer-1";
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+ reg = <0x200000 0x100000>;
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+ clocks = <&display_clocks CLK_BUS_MIXER1>,
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+ <&display_clocks CLK_MIXER1>;
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+ clock-names = "bus",
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+ "mod";
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+ resets = <&display_clocks RST_MIXER1>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ mixer1_out: port@1 {
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+ reg = <1>;
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+
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+ mixer1_out_tcon1: endpoint {
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+ remote-endpoint = <&tcon1_in_mixer1>;
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+ };
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+ };
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+ };
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+ };
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+ };
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+
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syscon: syscon@1c00000 {
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- compatible = "allwinner,sun50i-a64-system-controller",
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+ compatible = "allwinner,sun50i-a64-system-control",
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"syscon";
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reg = <0x01c00000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ sram_c: sram@18000 {
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+ compatible = "mmio-sram";
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+ reg = <0x00018000 0x28000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0x00018000 0x28000>;
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+
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+ de2_sram: sram-section@0 {
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+ compatible = "allwinner,sun50i-a64-sram-c";
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+ reg = <0x0000 0x28000>;
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+ };
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+ };
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};
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dma: dma-controller@1c02000 {
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@@ -185,6 +291,75 @@
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#dma-cells = <1>;
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};
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+ tcon0: lcd-controller@1c0c000 {
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+ compatible = "allwinner,sun50i-a64-tcon-lcd",
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+ "allwinner,sun8i-a83t-tcon-lcd";
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+ reg = <0x01c0c000 0x1000>;
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+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
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+ clock-names = "ahb", "tcon-ch0";
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+ clock-output-names = "tcon-pixel-clock";
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+ resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
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+ reset-names = "lcd", "lvds";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ tcon0_in: port@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+
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+ tcon0_in_mixer0: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&mixer0_out_tcon0>;
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+ };
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+ };
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+
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+ tcon0_out: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+ };
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+ };
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+ };
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+
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+ tcon1: lcd-controller@1c0d000 {
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+ compatible = "allwinner,sun50i-a64-tcon-tv",
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+ "allwinner,sun8i-a83t-tcon-tv";
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+ reg = <0x01c0d000 0x1000>;
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+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
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+ clock-names = "ahb", "tcon-ch1";
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+ resets = <&ccu RST_BUS_TCON1>;
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+ reset-names = "lcd";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ tcon1_in: port@0 {
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+ reg = <0>;
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+
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+ tcon1_in_mixer1: endpoint {
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+ remote-endpoint = <&mixer1_out_tcon1>;
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+ };
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+ };
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+
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+ tcon1_out: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+
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+ tcon1_out_hdmi: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&hdmi_in_tcon1>;
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+ };
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+ };
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+ };
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+ };
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+
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun50i-a64-mmc";
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reg = <0x01c0f000 0x1000>;
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@@ -227,6 +402,11 @@
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#size-cells = <0>;
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};
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+ sid: eeprom@1c14000 {
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+ compatible = "allwinner,sun50i-a64-sid";
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+ reg = <0x1c14000 0x400>;
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+ };
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+
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usb_otg: usb@1c19000 {
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compatible = "allwinner,sun8i-a33-musb";
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reg = <0x01c19000 0x0400>;
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@@ -356,7 +536,7 @@
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};
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mmc2_pins: mmc2-pins {
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- pins = "PC1", "PC5", "PC6", "PC8", "PC9",
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+ pins = "PC5", "PC6", "PC8", "PC9",
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"PC10","PC11", "PC12", "PC13",
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"PC14", "PC15", "PC16";
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function = "mmc2";
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@@ -364,6 +544,18 @@
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bias-pull-up;
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};
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+ mmc2_ds_pin: mmc2-ds-pin {
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+ pins = "PC1";
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+ function = "mmc2";
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+ drive-strength = <30>;
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+ bias-pull-up;
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+ };
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+
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+ pwm_pin: pwm_pin {
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+ pins = "PD22";
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+ function = "pwm";
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+ };
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+
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rmii_pins: rmii_pins {
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pins = "PD10", "PD11", "PD13", "PD14", "PD17",
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"PD18", "PD19", "PD20", "PD22", "PD23";
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@@ -394,7 +586,7 @@
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function = "spi1";
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};
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- uart0_pins_a: uart0 {
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+ uart0_pb_pins: uart0-pb-pins {
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pins = "PB8", "PB9";
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function = "uart0";
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};
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@@ -474,15 +666,6 @@
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status = "disabled";
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};
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- pwm: pwm@1c21400 {
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- compatible = "allwinner,sun50i-a64-pwm",
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- "allwinner,sun5i-a13-pwm";
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- reg = <0x01c21400 0x8>;
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- clocks = <&osc24M>;
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- #pwm-cells = <3>;
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- status = "disabled";
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- };
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-
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uart0: serial@1c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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@@ -617,8 +800,6 @@
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clocks = <&ccu CLK_BUS_EMAC>;
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clock-names = "stmmaceth";
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status = "disabled";
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- #address-cells = <1>;
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- #size-cells = <0>;
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mdio: mdio {
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compatible = "snps,dwmac-mdio";
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@@ -638,11 +819,69 @@
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#interrupt-cells = <3>;
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};
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+ pwm: pwm@1c21400 {
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+ compatible = "allwinner,sun50i-a64-pwm",
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+ "allwinner,sun5i-a13-pwm";
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+ reg = <0x01c21400 0x400>;
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+ clocks = <&osc24M>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pwm_pin>;
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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+ hdmi: hdmi@1ee0000 {
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+ compatible = "allwinner,sun50i-a64-dw-hdmi",
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+ "allwinner,sun8i-a83t-dw-hdmi";
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+ reg = <0x01ee0000 0x10000>;
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+ reg-io-width = <1>;
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+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
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+ <&ccu CLK_HDMI>;
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+ clock-names = "iahb", "isfr", "tmds";
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+ resets = <&ccu RST_BUS_HDMI1>;
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+ reset-names = "ctrl";
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+ phys = <&hdmi_phy>;
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+ phy-names = "hdmi-phy";
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+ status = "disabled";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ hdmi_in: port@0 {
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+ reg = <0>;
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+
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+ hdmi_in_tcon1: endpoint {
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+ remote-endpoint = <&tcon1_out_hdmi>;
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+ };
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+ };
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+
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+ hdmi_out: port@1 {
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+ reg = <1>;
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+ };
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+ };
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+ };
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+
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+ hdmi_phy: hdmi-phy@1ef0000 {
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+ compatible = "allwinner,sun50i-a64-hdmi-phy";
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+ reg = <0x01ef0000 0x10000>;
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+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
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+ <&ccu 7>;
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+ clock-names = "bus", "mod", "pll-0";
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+ resets = <&ccu RST_BUS_HDMI0>;
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+ reset-names = "phy";
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+ #phy-cells = <0>;
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+ };
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+
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rtc: rtc@1f00000 {
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compatible = "allwinner,sun6i-a31-rtc";
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reg = <0x01f00000 0x54>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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+ clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
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+ clocks = <&osc32k>;
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+ #clock-cells = <1>;
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};
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r_intc: interrupt-controller@1f00c00 {
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@@ -664,6 +903,29 @@
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#reset-cells = <1>;
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};
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+ r_i2c: i2c@1f02400 {
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+ compatible = "allwinner,sun50i-a64-i2c",
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+ "allwinner,sun6i-a31-i2c";
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+ reg = <0x01f02400 0x400>;
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+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&r_ccu CLK_APB0_I2C>;
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+ resets = <&r_ccu RST_APB0_I2C>;
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|
|
+ status = "disabled";
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|
|
+ #address-cells = <1>;
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|
|
+ #size-cells = <0>;
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|
|
+ };
|
|
|
+
|
|
|
+ r_pwm: pwm@1f03800 {
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|
|
+ compatible = "allwinner,sun50i-a64-pwm",
|
|
|
+ "allwinner,sun5i-a13-pwm";
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|
|
+ reg = <0x01f03800 0x400>;
|
|
|
+ clocks = <&osc24M>;
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|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&r_pwm_pin>;
|
|
|
+ #pwm-cells = <3>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
r_pio: pinctrl@1f02c00 {
|
|
|
compatible = "allwinner,sun50i-a64-r-pinctrl";
|
|
|
reg = <0x01f02c00 0x400>;
|
|
@@ -675,6 +937,16 @@
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|
|
interrupt-controller;
|
|
|
#interrupt-cells = <3>;
|
|
|
|
|
|
+ r_i2c_pl89_pins: r-i2c-pl89-pins {
|
|
|
+ pins = "PL8", "PL9";
|
|
|
+ function = "s_i2c";
|
|
|
+ };
|
|
|
+
|
|
|
+ r_pwm_pin: pwm {
|
|
|
+ pins = "PL10";
|
|
|
+ function = "s_pwm";
|
|
|
+ };
|
|
|
+
|
|
|
r_rsb_pins: rsb {
|
|
|
pins = "PL0", "PL1";
|
|
|
function = "s_rsb";
|