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@@ -171,91 +171,75 @@ static struct module_pin_mux mii1_pin_mux[] = {
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{-1},
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};
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+#ifdef CONFIG_NAND
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static struct module_pin_mux nand_pin_mux[] = {
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- {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
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- {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
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- {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
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- {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
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- {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
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- {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
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- {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
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- {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
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- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
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- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
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- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
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- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
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- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
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- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
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- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
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+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
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+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
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+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
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+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
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+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
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+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
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+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
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+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
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+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
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+ {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
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+ {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
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+ {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
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+ {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
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+ {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
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+ {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
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+ {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
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+ {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
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+#endif
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+ {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
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+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */
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+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */
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+ {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */
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+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */
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+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */
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+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
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{-1},
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};
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-
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-#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
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+#elif defined(CONFIG_NOR)
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static struct module_pin_mux bone_norcape_pin_mux[] = {
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- {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */
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- {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */
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- {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */
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- {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */
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- {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */
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- {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */
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- {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */
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- {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */
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- {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */
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- {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */
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- {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */
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- {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
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- {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */
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- {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */
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- {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */
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- {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */
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- {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */
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- {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */
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- {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */
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- {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */
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- {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */
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- {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */
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- {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */
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- {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */
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- {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */
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- {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */
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- {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */
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- {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */
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- {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */
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- {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */
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- {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */
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- {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */
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- {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */
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- {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */
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- {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */
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- {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */
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-
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- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */
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- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
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- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
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- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
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- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */
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- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
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+ {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */
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+ {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */
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+ {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */
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+ {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */
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+ {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */
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+ {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */
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+ {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */
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+ {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */
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+ {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */
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+ {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */
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+ {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */
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+ {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */
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+ {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */
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+ {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */
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+ {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */
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+ {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */
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+ {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */
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+ {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */
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+ {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */
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+ {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */
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+ {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */
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+ {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */
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+ {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */
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+ {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */
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+ {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */
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+ {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
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+ {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
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+ {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
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+ {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */
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+ {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
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{-1},
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};
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#endif
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#if defined(CONFIG_NOR_BOOT)
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-static struct module_pin_mux norboot_pin_mux[] = {
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- {OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
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- {OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
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- {OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
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- {OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
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- {OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
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- {OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
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- {OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
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- {OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
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- {OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
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- {-1},
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-};
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-
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void enable_norboot_pin_mux(void)
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{
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- configure_module_pin_mux(norboot_pin_mux);
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+ configure_module_pin_mux(bone_norcape_pin_mux);
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}
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#endif
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@@ -336,11 +320,12 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
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configure_module_pin_mux(i2c1_pin_mux);
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configure_module_pin_mux(mii1_pin_mux);
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configure_module_pin_mux(mmc0_pin_mux);
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-#ifndef CONFIG_NOR
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- configure_module_pin_mux(mmc1_pin_mux);
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-#endif
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-#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
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+#if defined(CONFIG_NAND)
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+ configure_module_pin_mux(nand_pin_mux);
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+#elif defined(CONFIG_NOR)
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configure_module_pin_mux(bone_norcape_pin_mux);
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+#else
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+ configure_module_pin_mux(mmc1_pin_mux);
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#endif
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} else if (board_is_gp_evm(header)) {
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/* General Purpose EVM */
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@@ -351,19 +336,16 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
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if (profile & ~PROFILE_2)
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configure_module_pin_mux(i2c1_pin_mux);
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/* Profiles 2 & 3 don't have NAND */
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+#ifdef CONFIG_NAND
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if (profile & ~(PROFILE_2 | PROFILE_3))
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configure_module_pin_mux(nand_pin_mux);
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+#endif
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else if (profile == PROFILE_2) {
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configure_module_pin_mux(mmc1_pin_mux);
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configure_module_pin_mux(spi0_pin_mux);
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}
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} else if (board_is_idk(header)) {
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- /*
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- * Industrial Motor Control (IDK)
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- * note: IDK console is on UART3 by default.
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- * So u-boot mus be build with CONFIG_SERIAL4 and
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- * CONFIG_CONS_INDEX=4
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- */
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+ /* Industrial Motor Control (IDK) */
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configure_module_pin_mux(mii1_pin_mux);
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configure_module_pin_mux(mmc0_no_cd_pin_mux);
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} else if (board_is_evm_sk(header)) {
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@@ -377,7 +359,13 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
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configure_module_pin_mux(i2c1_pin_mux);
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configure_module_pin_mux(mii1_pin_mux);
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configure_module_pin_mux(mmc0_pin_mux);
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+#if defined(CONFIG_NAND)
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+ configure_module_pin_mux(nand_pin_mux);
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+#elif defined(CONFIG_NOR)
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+ configure_module_pin_mux(bone_norcape_pin_mux);
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+#else
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configure_module_pin_mux(mmc1_pin_mux);
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+#endif
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} else {
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puts("Unknown board, cannot configure pinmux.");
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hang();
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