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@@ -87,6 +87,8 @@ void pciauto_setup_device(struct pci_controller *hose,
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pci_size_t bar_size;
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pci_size_t bar_size;
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u16 cmdstat = 0;
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u16 cmdstat = 0;
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int bar, bar_nr = 0;
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int bar, bar_nr = 0;
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+ u8 header_type;
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+ int rom_addr;
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#ifndef CONFIG_PCI_ENUM_ONLY
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#ifndef CONFIG_PCI_ENUM_ONLY
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pci_addr_t bar_value;
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pci_addr_t bar_value;
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struct pci_region *bar_res;
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struct pci_region *bar_res;
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@@ -182,38 +184,32 @@ void pciauto_setup_device(struct pci_controller *hose,
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bar_nr++;
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bar_nr++;
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}
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}
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+ /* Configure the expansion ROM address */
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+ pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
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+ if (header_type != PCI_HEADER_TYPE_CARDBUS) {
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+ rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
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+ PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
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+ pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
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+ pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
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+ if (bar_response) {
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+ bar_size = -(bar_response & ~1);
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+ DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size);
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+ if (pciauto_region_allocate(mem, bar_size,
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+ &bar_value) == 0) {
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+ pci_hose_write_config_dword(hose, dev, rom_addr,
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+ bar_value);
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+ }
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+ cmdstat |= PCI_COMMAND_MEMORY;
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+ DEBUGF("\n");
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+ }
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+ }
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+
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
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CONFIG_SYS_PCI_CACHE_LINE_SIZE);
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CONFIG_SYS_PCI_CACHE_LINE_SIZE);
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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}
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}
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-int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev)
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-{
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- pci_addr_t bar_value;
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- pci_size_t bar_size;
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- u32 bar_response;
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- u16 cmdstat = 0;
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-
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- pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, 0xfffffffe);
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- pci_hose_read_config_dword(hose, dev, PCI_ROM_ADDRESS, &bar_response);
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- if (!bar_response)
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- return -ENOENT;
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-
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- bar_size = -(bar_response & ~1);
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- DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size);
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- if (pciauto_region_allocate(hose->pci_mem, bar_size, &bar_value) == 0) {
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- pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS,
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- bar_value);
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- }
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- DEBUGF("\n");
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- pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
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- cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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- pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
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-
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- return 0;
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-}
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-
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void pciauto_prescan_setup_bridge(struct pci_controller *hose,
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void pciauto_prescan_setup_bridge(struct pci_controller *hose,
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pci_dev_t dev, int sub_bus)
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pci_dev_t dev, int sub_bus)
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{
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{
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