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@@ -109,7 +109,7 @@ DECLARE_GLOBAL_DATA_PTR;
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#define QSPISRC_PER_CK 3
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#define PWR_CR3 0x0c
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-#define PWR_CR3_SDEN BIT(2)
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+#define PWR_CR3_SCUEN BIT(2)
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#define PWR_D3CR 0x18
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#define PWR_D3CR_VOS_MASK GENMASK(15, 14)
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#define PWR_D3CR_VOS_SHIFT 14
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@@ -361,11 +361,11 @@ int configure_clocks(struct udevice *dev)
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writel(0x0, ®s->d2ccip1r);
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writel(0x0, ®s->d2ccip2r);
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- /* Set voltage scaling at scale 1 */
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+ /* Set voltage scaling at scale 1 (1,15 - 1,26 Volts) */
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clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK,
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VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT);
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- /* disable step down converter */
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- clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SDEN);
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+ /* Lock supply configuration update */
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+ clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN);
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while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY))
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;
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