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@@ -12,6 +12,7 @@
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#include <dm.h>
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#include <dm/uclass-internal.h>
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#include <asm/acpi_table.h>
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+#include <asm/io.h>
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#include <asm/lapic.h>
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#include <asm/tables.h>
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@@ -301,6 +302,25 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
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header->checksum = table_compute_checksum((void *)mcfg, header->length);
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}
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+static void enter_acpi_mode(int pm1_cnt)
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+{
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+ /*
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+ * PM1_CNT register bit0 selects the power management event to be
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+ * either an SCI or SMI interrupt. When this bit is set, then power
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+ * management events will generate an SCI interrupt. When this bit
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+ * is reset power management events will generate an SMI interrupt.
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+ *
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+ * Per ACPI spec, it is the responsibility of the hardware to set
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+ * or reset this bit. OSPM always preserves this bit position.
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+ *
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+ * U-Boot does not support SMI. And we don't have plan to support
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+ * anything running in SMM within U-Boot. To create a legacy-free
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+ * system, and expose ourselves to OSPM as working under ACPI mode
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+ * already, turn this bit on.
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+ */
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+ outw(PM1_CNT_SCI_EN, pm1_cnt);
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+}
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+
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/*
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* QEMU's version of write_acpi_tables is defined in
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* arch/x86/cpu/qemu/acpi_table.c
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@@ -400,5 +420,11 @@ u32 write_acpi_tables(u32 start)
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debug("ACPI: done\n");
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+ /*
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+ * Other than waiting for OSPM to request us to switch to ACPI mode,
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+ * do it by ourselves, since SMI will not be triggered.
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+ */
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+ enter_acpi_mode(fadt->pm1a_cnt_blk);
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+
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return current;
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}
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