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@@ -14,12 +14,12 @@
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#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
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#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
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#define XPAR_INTC_0_BASEADDR 0x81800000
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#define XPAR_INTC_0_BASEADDR 0x81800000
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#define XPAR_SPI_0_BASEADDR 0x83400000
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#define XPAR_SPI_0_BASEADDR 0x83400000
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-#define XPAR_UARTLITE_0_BASEADDR 0x84000000
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#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
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#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
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#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
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#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
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#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
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#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
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-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
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-#define XPAR_UARTLITE_0_BAUDRATE 9600
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+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
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#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
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#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
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+#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef
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+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
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#endif
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#endif
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