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@@ -185,10 +185,6 @@ void init_pll(const struct pll_init_data *data)
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tmp &= ~(PLL_BWADJ_HI_MASK);
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tmp &= ~(PLL_BWADJ_HI_MASK);
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tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
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tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
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- /* set PLL Select (bit 13) for PASS PLL */
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- if (data->pll == PASS_PLL)
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- tmp |= PLLCTL_PAPLL;
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-
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__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
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__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
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/* Reset bit: bit 14 for both DDR3 & PASS PLL */
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/* Reset bit: bit 14 for both DDR3 & PASS PLL */
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@@ -261,3 +257,16 @@ inline int get_max_arm_speed(void)
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return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
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return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
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}
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}
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#endif
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#endif
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+
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+void pass_pll_pa_clk_enable(void)
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+{
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+ u32 reg;
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+
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+ reg = readl(keystone_pll_regs[PASS_PLL].reg1);
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+
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+ reg |= PLLCTL_PAPLL;
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+ writel(reg, keystone_pll_regs[PASS_PLL].reg1);
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+
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+ /* wait till clock is enabled */
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+ sdelay(15000);
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+}
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