sandbox: Enable support for MC34708 PMIC in DTS

This commit also provides the default values of the emulated MC34708 PMIC
internal registers content.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

arch/sandbox/dts/sandbox.dts

@@ -115,6 +115,10 @@
 		sandbox_pmic: sandbox_pmic {
 			reg = <0x40>;
 		};
+
+		mc34708: pmic@41 {
+			reg = <0x41>;
+		};
 	};
 
 	lcd {

arch/sandbox/dts/sandbox64.dts

@@ -115,6 +115,10 @@
 		sandbox_pmic: sandbox_pmic {
 			reg = <0x40>;
 		};
+
+		mc34708: pmic@41 {
+			reg = <0x41>;
+		};
 	};
 
 	lcd {

arch/sandbox/dts/sandbox_pmic.dtsi

@@ -81,3 +81,36 @@
 		regulator-max-microvolt = <1500000>;
 	};
 };
+
+&mc34708 {
+	compatible = "fsl,mc34708";
+
+	pmic_emul {
+		compatible = "sandbox,i2c-pmic";
+
+		reg-defaults = /bits/ 8 <
+			0x00 0x80 0x08 0xff 0xff 0xff 0x2e 0x01 0x08
+			0x40 0x80 0x81 0x5f 0xff 0xfb 0x1e 0x80 0x18
+			0x00 0x00 0x0e 0x00 0x00 0x14 0x00 0x00 0x00
+			0x00 0x00 0x20 0x00 0x01 0x3a 0x00 0x00 0x00
+			0x00 0x00 0x00 0x00 0x00 0x40 0x00 0x00 0x00
+			0x42 0x21 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+			0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x5f
+			0x01 0xff 0xff 0x00 0x00 0x00 0x00 0x7f 0xff
+			0x92 0x49 0x24 0x59 0x6d 0x34 0x18 0xc1 0x8c
+			0x00 0x60 0x18 0x51 0x48 0x45 0x14 0x51 0x45
+			0x00 0x06 0x32 0x00 0x00 0x00 0x06 0x9c 0x99
+			0x00 0x38 0x0a 0x00 0x38 0x0a 0x00 0x38 0x0a
+			0x00 0x38 0x0a 0x84 0x00 0x00 0x00 0x00 0x00
+			0x80 0x90 0x8f 0xf8 0x00 0x04 0x00 0x00 0x00
+			0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+			0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+			0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+			0x01 0x31 0x7e 0x2b 0x03 0xfd 0xc0 0x36 0x1b
+			0x60 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+			0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+			0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+			0x00 0x00 0x00
+		>;
+	};
+};

arch/sandbox/dts/test.dts

@@ -227,6 +227,10 @@
 		sandbox_pmic: sandbox_pmic {
 			reg = <0x40>;
 		};
+
+		mc34708: pmic@41 {
+			reg = <0x41>;
+		};
 	};
 
 	adc@0 {