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@@ -389,33 +389,6 @@ struct ccsr_serdes {
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u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
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};
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-
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-
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-/* AHCI (sata) register map */
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-struct ccsr_ahci {
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- u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
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- u32 pcfg; /* port config */
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- u32 ppcfg; /* port phy1 config */
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- u32 pp2c; /* port phy2 config */
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- u32 pp3c; /* port phy3 config */
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- u32 pp4c; /* port phy4 config */
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- u32 pp5c; /* port phy5 config */
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- u32 paxic; /* port AXI config */
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- u32 axicc; /* AXI cache control */
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- u32 axipc; /* AXI PROT control */
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- u32 ptc; /* port Trans Config */
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- u32 pts; /* port Trans Status */
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- u32 plc; /* port link config */
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- u32 plc1; /* port link config1 */
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- u32 plc2; /* port link config2 */
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- u32 pls; /* port link status */
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- u32 pls1; /* port link status1 */
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- u32 pcmdc; /* port CMD config */
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- u32 ppcs; /* port phy control status */
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- u32 pberr; /* port 0/1 BIST error */
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- u32 cmds; /* port 0/1 CMD status error */
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-};
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-
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#define RCPM_POWMGTCSR 0x130
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#define RCPM_POWMGTCSR_SERDES_PW 0x80000000
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#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000
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