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@@ -35,6 +35,7 @@
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*/
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#include <common.h>
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+#include <i2c.h>
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#include <asm/arch/i2c.h>
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#include <asm/io.h>
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@@ -48,22 +49,14 @@ DECLARE_GLOBAL_DATA_PTR;
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/* Absolutely safe for status update at 100 kHz I2C: */
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#define I2C_WAIT 200
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-static int wait_for_bb(void);
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-static u16 wait_for_event(void);
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-static void flush_fifo(void);
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+static int wait_for_bb(struct i2c_adapter *adap);
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+static struct i2c *omap24_get_base(struct i2c_adapter *adap);
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+static u16 wait_for_event(struct i2c_adapter *adap);
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+static void flush_fifo(struct i2c_adapter *adap);
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-/*
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- * For SPL boot some boards need i2c before SDRAM is initialised so force
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- * variables to live in SRAM
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- */
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-static struct i2c __attribute__((section (".data"))) *i2c_base =
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- (struct i2c *)I2C_DEFAULT_BASE;
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-static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] =
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- { [0 ... (I2C_BUS_MAX-1)] = 0 };
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-static unsigned int __attribute__((section (".data"))) current_bus = 0;
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-
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-void i2c_init(int speed, int slaveadd)
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+static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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{
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+ struct i2c *i2c_base = omap24_get_base(adap);
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int psc, fsscll, fssclh;
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int hsscll = 0, hssclh = 0;
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u32 scll, sclh;
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@@ -163,16 +156,15 @@ void i2c_init(int speed, int slaveadd)
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I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
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#endif
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udelay(1000);
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- flush_fifo();
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+ flush_fifo(adap);
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writew(0xFFFF, &i2c_base->stat);
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writew(0, &i2c_base->cnt);
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-
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- if (gd->flags & GD_FLG_RELOC)
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- bus_initialized[current_bus] = 1;
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}
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-static void flush_fifo(void)
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-{ u16 stat;
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+static void flush_fifo(struct i2c_adapter *adap)
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+{
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+ struct i2c *i2c_base = omap24_get_base(adap);
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+ u16 stat;
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/* note: if you try and read data when its not there or ready
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* you get a bus error
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@@ -192,8 +184,9 @@ static void flush_fifo(void)
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* i2c_probe: Use write access. Allows to identify addresses that are
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* write-only (like the config register of dual-port EEPROMs)
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*/
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-int i2c_probe(uchar chip)
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+static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
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{
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+ struct i2c *i2c_base = omap24_get_base(adap);
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u16 status;
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int res = 1; /* default = fail */
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@@ -201,7 +194,7 @@ int i2c_probe(uchar chip)
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return res;
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/* Wait until bus is free */
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- if (wait_for_bb())
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+ if (wait_for_bb(adap))
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return res;
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/* No data transfer, slave addr only */
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@@ -212,7 +205,7 @@ int i2c_probe(uchar chip)
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writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
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I2C_CON_STP, &i2c_base->con);
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- status = wait_for_event();
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+ status = wait_for_event(adap);
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if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
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/*
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@@ -223,7 +216,7 @@ int i2c_probe(uchar chip)
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*/
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if (status == I2C_STAT_XRDY)
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printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
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- current_bus, status);
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+ adap->hwadapnr, status);
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goto pr_exit;
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}
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@@ -239,7 +232,7 @@ int i2c_probe(uchar chip)
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I2C_CON_STP, &i2c_base->con); /* STP */
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}
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pr_exit:
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- flush_fifo();
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+ flush_fifo(adap);
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writew(0xFFFF, &i2c_base->stat);
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writew(0, &i2c_base->cnt);
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return res;
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@@ -258,8 +251,10 @@ pr_exit:
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* or that do not need a register address at all (such as some clock
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* distributors).
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*/
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-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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+static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
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+ int alen, uchar *buffer, int len)
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{
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+ struct i2c *i2c_base = omap24_get_base(adap);
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int i2c_error = 0;
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u16 status;
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@@ -287,7 +282,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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}
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/* Wait until bus not busy */
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- if (wait_for_bb())
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+ if (wait_for_bb(adap))
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return 1;
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/* Zero, one or two bytes reg address (offset) */
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@@ -308,12 +303,12 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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#endif
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/* Send register offset */
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while (1) {
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- status = wait_for_event();
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+ status = wait_for_event(adap);
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/* Try to identify bus that is not padconf'd for I2C */
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if (status == I2C_STAT_XRDY) {
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i2c_error = 2;
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printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
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- current_bus, status);
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+ adap->hwadapnr, status);
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goto rd_exit;
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}
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if (status == 0 || status & I2C_STAT_NACK) {
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@@ -348,7 +343,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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/* Receive data */
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while (1) {
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- status = wait_for_event();
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+ status = wait_for_event(adap);
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/*
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* Try to identify bus that is not padconf'd for I2C. This
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* state could be left over from previous transactions if
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@@ -357,7 +352,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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if (status == I2C_STAT_XRDY) {
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i2c_error = 2;
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printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
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- current_bus, status);
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+ adap->hwadapnr, status);
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goto rd_exit;
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}
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if (status == 0 || status & I2C_STAT_NACK) {
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@@ -375,15 +370,17 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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}
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rd_exit:
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- flush_fifo();
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+ flush_fifo(adap);
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writew(0xFFFF, &i2c_base->stat);
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writew(0, &i2c_base->cnt);
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return i2c_error;
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}
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/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
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-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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+static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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+ int alen, uchar *buffer, int len)
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{
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+ struct i2c *i2c_base = omap24_get_base(adap);
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int i;
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u16 status;
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int i2c_error = 0;
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@@ -415,7 +412,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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}
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/* Wait until bus not busy */
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- if (wait_for_bb())
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+ if (wait_for_bb(adap))
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return 1;
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/* Start address phase - will write regoffset + len bytes data */
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@@ -428,12 +425,12 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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while (alen) {
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/* Must write reg offset (one or two bytes) */
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- status = wait_for_event();
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+ status = wait_for_event(adap);
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/* Try to identify bus that is not padconf'd for I2C */
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if (status == I2C_STAT_XRDY) {
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i2c_error = 2;
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printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
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- current_bus, status);
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+ adap->hwadapnr, status);
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goto wr_exit;
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}
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if (status == 0 || status & I2C_STAT_NACK) {
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@@ -455,7 +452,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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}
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/* Address phase is over, now write data */
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for (i = 0; i < len; i++) {
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- status = wait_for_event();
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+ status = wait_for_event(adap);
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if (status == 0 || status & I2C_STAT_NACK) {
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i2c_error = 1;
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printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
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@@ -474,7 +471,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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}
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wr_exit:
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- flush_fifo();
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+ flush_fifo(adap);
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writew(0xFFFF, &i2c_base->stat);
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writew(0, &i2c_base->cnt);
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return i2c_error;
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@@ -484,8 +481,9 @@ wr_exit:
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* Wait for the bus to be free by checking the Bus Busy (BB)
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* bit to become clear
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*/
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-static int wait_for_bb(void)
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+static int wait_for_bb(struct i2c_adapter *adap)
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{
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+ struct i2c *i2c_base = omap24_get_base(adap);
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int timeout = I2C_TIMEOUT;
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u16 stat;
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@@ -514,8 +512,9 @@ static int wait_for_bb(void)
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* Wait for the I2C controller to complete current action
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* and update status
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*/
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-static u16 wait_for_event(void)
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+static u16 wait_for_event(struct i2c_adapter *adap)
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{
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+ struct i2c *i2c_base = omap24_get_base(adap);
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u16 status;
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int timeout = I2C_TIMEOUT;
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@@ -540,7 +539,7 @@ static u16 wait_for_event(void)
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* not been configured for I2C, and/or pull-ups are missing.
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*/
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printf("Check if pads/pull-ups of bus %d are properly configured\n",
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- current_bus);
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+ adap->hwadapnr);
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writew(0xFFFF, &i2c_base->stat);
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status = 0;
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}
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@@ -548,48 +547,93 @@ static u16 wait_for_event(void)
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return status;
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}
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-int i2c_set_bus_num(unsigned int bus)
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+static struct i2c *omap24_get_base(struct i2c_adapter *adap)
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{
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- if (bus >= I2C_BUS_MAX) {
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- printf("Bad bus: %x\n", bus);
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- return -1;
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- }
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-
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- switch (bus) {
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- default:
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- bus = 0; /* Fall through */
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+ switch (adap->hwadapnr) {
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case 0:
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- i2c_base = (struct i2c *)I2C_BASE1;
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+ return (struct i2c *)I2C_BASE1;
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break;
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case 1:
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- i2c_base = (struct i2c *)I2C_BASE2;
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+ return (struct i2c *)I2C_BASE2;
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break;
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#if (I2C_BUS_MAX > 2)
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case 2:
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- i2c_base = (struct i2c *)I2C_BASE3;
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+ return (struct i2c *)I2C_BASE3;
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break;
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#if (I2C_BUS_MAX > 3)
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case 3:
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- i2c_base = (struct i2c *)I2C_BASE4;
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+ return (struct i2c *)I2C_BASE4;
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break;
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#if (I2C_BUS_MAX > 4)
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case 4:
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- i2c_base = (struct i2c *)I2C_BASE5;
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+ return (struct i2c *)I2C_BASE5;
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break;
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#endif
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#endif
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#endif
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+ default:
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+ printf("wrong hwadapnr: %d\n", adap->hwadapnr);
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+ break;
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}
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+ return NULL;
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+}
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- current_bus = bus;
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+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
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+#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
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+#endif
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+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
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+#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
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+#endif
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- if (!bus_initialized[current_bus])
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- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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+U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
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+ omap24_i2c_read, omap24_i2c_write, NULL,
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+ CONFIG_SYS_OMAP24_I2C_SPEED,
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+ CONFIG_SYS_OMAP24_I2C_SLAVE,
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+ 0)
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+U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
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+ omap24_i2c_read, omap24_i2c_write, NULL,
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+ CONFIG_SYS_OMAP24_I2C_SPEED1,
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+ CONFIG_SYS_OMAP24_I2C_SLAVE1,
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+ 1)
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+#if (I2C_BUS_MAX > 2)
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+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
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+#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
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+#endif
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+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
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+#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
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+#endif
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- return 0;
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-}
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+U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
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+ omap24_i2c_read, omap24_i2c_write, NULL,
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+ CONFIG_SYS_OMAP24_I2C_SPEED2,
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+ CONFIG_SYS_OMAP24_I2C_SLAVE2,
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+ 2)
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+#if (I2C_BUS_MAX > 3)
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+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
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+#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
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+#endif
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+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
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+#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
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+#endif
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-int i2c_get_bus_num(void)
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-{
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- return (int) current_bus;
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-}
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+U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
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+ omap24_i2c_read, omap24_i2c_write, NULL,
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+ CONFIG_SYS_OMAP24_I2C_SPEED3,
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+ CONFIG_SYS_OMAP24_I2C_SLAVE3,
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+ 3)
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+#if (I2C_BUS_MAX > 4)
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+#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
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+#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
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+#endif
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+#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
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+#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
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+#endif
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+
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+U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
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+ omap24_i2c_read, omap24_i2c_write, NULL,
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+ CONFIG_SYS_OMAP24_I2C_SPEED4,
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+ CONFIG_SYS_OMAP24_I2C_SLAVE4,
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+ 4)
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|
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+#endif
|
|
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+#endif
|
|
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+#endif
|
Heiko Schocher