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@@ -1,7 +1,7 @@
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The common CFI driver provides this weak default implementation for
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The common CFI driver provides this weak default implementation for
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flash_cmd_reset():
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flash_cmd_reset():
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-void __flash_cmd_reset(flash_info_t *info)
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+static void __flash_cmd_reset(flash_info_t *info)
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{
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{
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/*
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/*
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* We do not yet know what kind of commandset to use, so we issue
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* We do not yet know what kind of commandset to use, so we issue
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@@ -9,22 +9,43 @@ void __flash_cmd_reset(flash_info_t *info)
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* that AMD flash roms ignore the Intel command.
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* that AMD flash roms ignore the Intel command.
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*/
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*/
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flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
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flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
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+ udelay(1);
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flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
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flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
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}
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}
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void flash_cmd_reset(flash_info_t *info)
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void flash_cmd_reset(flash_info_t *info)
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__attribute__((weak,alias("__flash_cmd_reset")));
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__attribute__((weak,alias("__flash_cmd_reset")));
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+Some flash chips seem to have trouble with this reset sequence.
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+In this case, board-specific code can override this weak default
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+version with a board-specific function.
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-Some flash chips seems to have trouble with this reset sequence. In this case
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-the board specific code can override this weak default version with a board
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-specific function. For example the digsy_mtc board equipped with the M29W128GH
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-from Numonyx needs this version to function properly:
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+At the time of writing, there are two boards that define their own
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+routine for this.
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+
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+First, the digsy_mtc board equipped with the M29W128GH from Numonyx
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+needs this version to function properly:
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void flash_cmd_reset(flash_info_t *info)
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void flash_cmd_reset(flash_info_t *info)
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{
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{
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flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
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flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
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}
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}
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+In addition, the t3corp board defines the routine thusly:
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+
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+void flash_cmd_reset(flash_info_t *info)
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+{
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+ /*
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+ * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
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+ * needs the Spansion type reset commands. The other flash chip
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+ * is located behind a FPGA (Xilinx DS617) and needs the Intel type
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+ * reset command.
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+ */
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+ if (info->start[0] == CONFIG_SYS_FLASH_BASE)
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+ flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
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+ else
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+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
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+}
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+
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see also:
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see also:
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http://www.mail-archive.com/u-boot@lists.denx.de/msg24368.html
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http://www.mail-archive.com/u-boot@lists.denx.de/msg24368.html
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