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@@ -123,20 +123,6 @@ void sandybridge_early_init(int chipset_type)
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pci_dev_t pch_dev = PCH_DEV;
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pci_dev_t video_dev = PCH_VIDEO_DEV;
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pci_dev_t lpc_dev = PCH_LPC_DEV;
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- u32 capid0_a;
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- u8 reg8;
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-
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- /* Device ID Override Enable should be done very early */
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- capid0_a = x86_pci_read_config32(pch_dev, 0xe4);
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- if (capid0_a & (1 << 10)) {
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- reg8 = x86_pci_read_config8(pch_dev, 0xf3);
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- reg8 &= ~7; /* Clear 2:0 */
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-
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- if (chipset_type == SANDYBRIDGE_MOBILE)
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- reg8 |= 1; /* Set bit 0 */
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-
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- x86_pci_write_config8(pch_dev, 0xf3, reg8);
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- }
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/* Setup all BARs required for early PCIe and raminit */
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sandybridge_setup_bars(pch_dev, lpc_dev);
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@@ -149,6 +135,25 @@ void sandybridge_early_init(int chipset_type)
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static int bd82x6x_northbridge_probe(struct udevice *dev)
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{
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+ const int chipset_type = SANDYBRIDGE_MOBILE;
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+ u32 capid0_a;
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+ u8 reg8;
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+
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+ if (gd->flags & GD_FLG_RELOC)
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+ return 0;
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+
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+ /* Device ID Override Enable should be done very early */
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+ dm_pci_read_config32(dev, 0xe4, &capid0_a);
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+ if (capid0_a & (1 << 10)) {
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+ dm_pci_read_config8(dev, 0xf3, ®8);
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+ reg8 &= ~7; /* Clear 2:0 */
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+
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+ if (chipset_type == SANDYBRIDGE_MOBILE)
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+ reg8 |= 1; /* Set bit 0 */
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+
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+ dm_pci_write_config8(dev, 0xf3, reg8);
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+ }
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+
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return 0;
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}
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